JAJU821 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 サポート・リソース
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

2.1.1.1 Clocking Board Setup

Figure 2-1 shows the multichannel LMX2820 clocking board.

GUID-20211018-SS0I-SVTX-KHFR-J9DCXDMS7K3R-low.jpg Figure 2-1 Multichannel Clocking Board

Reference the following for clocking board setup:

  1. Power Supply

    Power supply connector J23: This connector is used to connect the power supply. Set the power supply to 12 V with a 3-A current limit.

  2. Input reference signals
    • Option 1: Connect the external reference signal to EXT_REF connector (J10). While connecting the external reference, disconnect the Y1 and U14/U37 connection by removing C29 and C316, and place C35. Disconnect the power supply of Y1 and U14 by removing jumpers J9 and J12. For reference enable to the clocking devices from the reference buffer device U13, place the short jumper at pin 2-3 of jumper J11.
    • Option 2: The onboard reference LMK61E2 (U14) is powered up using the jumper J12 and factory programmed to generate a 156-MHz LVDS output. U14 can be programmed to generate different clock frequencies using the I2C interface. LVDS output is translated to LVCMOS format using U37 and output enabled by shorting pin 1 of the jumpers J39-J40. While using the onboard LMK61E2, disconnect the clock inputs from Y1 and external reference by removing C29 and C35, then place C316. Isolate the power supply to Y1 by removing J9. For reference enable to clocking devices from reference buffer device U13, place the short jumper at pin 2-3 of jumper J11.
    • Option 3: The onboard VCXO Y1 is powered on using the jumper J9 and outputs a 122.88-MHz signal to the LMK04832 OSCin_P pin input. In this option, LMX2820 devices receive the reference signals from the LMK04832 DCLK ports. While using Y1, disconnect the clock inputs from LMK61E2 (U14) and external reference by removing C316, C35, C29, and R177, and place the R146 and R120. At the same time, isolate the power supply to U14 by removing the jumper J12.
    • Option 4: Use one of the previous options, when LMK04832 works in PLL mode. When LMK04832 is operating in distribution mode, connect the external reference to external connector J18 or J22 based on operating input frequency. While operating in distribution mode, power down the Y1 and U14 by removing jumpers J9 and J12.
  3. Input sync signal

    Connect the external sync signal at external J14 and J15 connectors to reset the LMK04832 dividers.

  4. Output signals
    • LMX2820 amplified outputs are generated at RFoutBP1 and RFoutBP2 connectors as DCLK and are connected to AFE7950EVMs as an external sampling clock.
    • SYSREFM1 and SYSREFM2 connectors generate the low-frequency SYSREF signals for AFE7950EVM.
    • Connectors J7 and J8 generate the FPGA CLKs and SYSREFs for two TSW14J56 capture cards.
  5. Programming interface

    Connect the USB mini cable to the onboard USB connector J29 and test the PC to program the LMX2820 clocking board devices using the clocking board software GUI.