JAJU821 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 サポート・リソース
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

1.2 System Description

Multichannel high-speed end equipment such as RADAR and electronic warfare systems have a critical clocking requirement to achieve better performance (high SNR, SFDR, IMD3, and so forth) of analog front end and low analog channel-to-channel skew.

Phased array radar contains high channel count transceiver systems, which need high dynamic range, wide transmitter and receiver bandwidth, low latency, and good synchronization between the transceiver channels. The signal chain solution based on the AFE7950 RF sampling transceiver, LMX2820, and LMK04832 devices are able to achieve optimum performance for phased array radar applications.

Electronic warfare equipment used as electronic protection, security, and attack also require a multichannel transceiver system with wide dynamic range and higher instantaneous bandwidth for higher range and speed. The AFE7950 device is a good fit for the multichannel transceiver requirements of the EW application, and this design shows the synchronization of multiple devices.

In this solution, two LMX2820 devices receive in-phase OSCin reference input signals from an external source or onboard LMK61E2 through the LMK1C1104 reference buffer and generate the two in-phase device clocks at 8847.36 MHz and SYSREFs at 1.92 MHz for the AFE7950EVM devices. LMK04832 is responsible to generate the two pair of in-phase FPGA reference clock and SYSREF for TSW14J56EVM capture cards. The LMK04832 device also provides the SYNC signal to two LMX2820 devices for synchronization to each other.

To meet the SYSREF setup and hold time for both AFE7950 devices, very low skew and phase-adjustable SYSREFs and device clocks are provided through the LMX2820 devices, which are responsible for low channel-to-channel skew between two AFEs.

This reference design demonstrates the multichannel low-noise JESD204B-compliant clock generation for two AFE7950 devices to synchronize them and make an 8T8R (8-transmit and 8-receive) system that is a good fit for phased-array RADAR, and electronic warfare applications.