JAJU821 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 サポート・リソース
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

2.3.4 Multiple AFE7950s TX and RX Alignment

Synchronized clocks are critical for multichannel systems. This section shows the multichannel synchronized clocking performance while measuring the channel-to-channel skew between the transmitter and receiver of the two AFE7950EVMs, respectively. The time-skew test is performed between the two channels of AFE7950EVMs at different frequencies operating in L and S band RADAR applications.

The skew of the transmitter channel is evaluated by measuring skew between the generated outputs of the DAC of each AFE in a high-speed oscilloscope. Table 2-5 shows the channel-to-channel skew at 8847.36-MHz DAC sampling frequency and the achieved skew was less than 5 ps for each output frequency.

Table 2-5 Measured TX Channel-to-Channel Skew
Operating Frequency Measured Time Skew (ps)
850 MHz 4.4
1800 MHz 5.3
2600 MHz 5.4

The skew of the receiver channel is evaluated by calculating the phase difference between signals captured from each ADC of the AFE. Table 2-6 shows the channel-to-channel skew at a 2949.12-MHz sampling frequency. The measured time skew was less than 10 ps for each input frequency.

Table 2-6 Measured RX Channel-to-Channel Skew
Operating Frequency Measured Time Skew (ps)
840 MHz 4.4
1750 MHz 0.31
2610 MHz 0.18
3700 MHz 3.56
4910 MHz 3.84