JAJU821 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 サポート・リソース
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization

The proposed LMX2820 clocking solution is interfaced with two AFE7950EVMs and two TSW14J56EVM capture cards to show the synchronization between multiple AFE7950 devices. Figure 2-2 shows the overall block diagram of the multiple transceiver synchronized system.

GUID-20211018-SS0I-MMTN-VFPD-VLDXQFB6C8CW-low.png Figure 2-2 TIDA-010230 Device Synchronization Block Diagram

Table 2-1 shows the AFE7950 operating modes and frequency requirements for various tests in this design.

Table 2-1 AFE7950 Mode Setup
Parameters \ Test TX Performance RX Performance Synchronization Test
Transmitter Mode 44210 - 44210
Interpolation 18 - 18
DAC Sampling Frequency (MHz) 8847.36 - 8847.36
Interpolated DAC clock rate (MHz) 491.52 - 491.52
K 16 - 16
F 2 - 2
Lane rate (Mbps) 9830.4 - 9830.4
Receiver Mode - 44210 24410
Decimation - 6 12
ADC Sampling Frequency (MHz) - 2949.12 2949.12
Decimated output rate (MHz) - 491.52 245.76
K - 16 32
F - 2 4
Lane rate (Mbps) - 9830.4 9830.4
SYSREF Frequency (MHz) 1.92 1.92 1.92
FPGA Clock (MHz) 245.76 245.76 245.76

The AFE7950EVM was tested with the proposed LMX2820 clocking solution for various test cases and modes to see the transmitter and receiver performance and compare with the data sheet performance along with a synchronization test for common frequency settings.