JAJU823 August   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
    4. 2.4 System Design Theory
      1. 2.4.1 Buck Converter Circuit Design Using TPS62903
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Startup
      2. 3.3.2 Load Transient
      3. 3.3.3 Output Ripple
      4. 3.3.4 Efficiency
      5. 3.3.5 Thermal Performance
      6. 3.3.6 Output Voltage vs. Output Current
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
        1. 4.1.3.1 Layout Prints
      4. 4.1.4 Altium Project
      5. 4.1.5 Gerber Files
      6. 4.1.6 Assembly Drawings
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

2.4.1 Buck Converter Circuit Design Using TPS62903

The TPS62903 is optimized to work within a range of external components. The LC output filters inductance and capacitance have to be considered together, creating a double pole, responsible for the corner frequency of the converter. See the TPS62903 data sheet for more details.



Figure 2-2 Buck Converter Circuit Design Using TPS62903

The TIDA-050052 is designed with a nominal 1-µH inductor to support 1.2-V output voltage. A shielded wire wound Inductor from Murata (DFE201612E-1R0M=P2) is used in this design. It has 4-A current saturation and 48-mΩ maximum DCR. 1-µH inductance is ideal for size and ripple given the VOUT of this design is only 1.2-V. Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on efficiency and transient response. Smaller values than 1-µH will cause a larger inductor current ripple which causes a larger negative inductor current in forced PWM mode at low or no output current.

A small low equivalent series resistance (ESR) multilayer ceramic capacitor (MLCC) is recommended to obtain the best filtering. For this design, a 10-µF/25V multilayer ceramic chip capacitor from Cal-Chip electronics (GMC21X7R106K25NT) is used as an input capacitor. It is designed to withstand up to 25-V which is enough for the input voltage range that we want to cover in this design.

For the output capacitor, the voltage rating is much smaller than the input, only 6-V to 10-V capacitor rating is needed. A 22-µF/10V multilayer ceramic chip capacitor (C2012X7S1A226M125AC) from TDK is chosen. Both the input and the output capacitors are X7R to cover the full temperature range of this design.

The MODE/S-CONF requires an E96 Resistor Series, 1% Accuracy, Temperature Coefficient better or equal than ±200- ppm/°C. A small size CRCW040226K1FKED from Vishay is used in this design.