JAJU835 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
      1.      10
    2. 2.2 Highlighted Products
      1. 2.2.1 DRV5056
      2. 2.2.2 DRV5032
      3. 2.2.3 TPS709
      4. 2.2.4 SN74HCS00
      5. 2.2.5 TPS22917
      6. 2.2.6 SN74AUP1G00
      7. 2.2.7 TLV9061
    3. 2.3 Design Considerations
      1. 2.3.1 Design Hardware Implementation
        1. 2.3.1.1 Hall-Effect Switches
          1. 2.3.1.1.1 U1 Wake-Up Sensor Configuration
          2. 2.3.1.1.2 U2 Stray-Field Sensor Configuration
          3. 2.3.1.1.3 U3 and U4 Tamper Sensor Configuration
          4. 2.3.1.1.4 Hall Switch Placement
            1. 2.3.1.1.4.1 Placement of U1 and U2 Sensors
              1. 2.3.1.1.4.1.1 U1 and U2 Magnetic Flux Density Estimation Results
            2. 2.3.1.1.4.2 Placement of U3 and U4 Hall Switches
              1. 2.3.1.1.4.2.1 U3 and U4 Magnetic Flux Density Estimation Results
          5. 2.3.1.1.5 Using Logic Gates to Combine Outputs from Hall-Effect Switches
        2. 2.3.1.2 Linear Hall-Effect Sensor Output
          1. 2.3.1.2.1 DRV5056 Power
          2. 2.3.1.2.2 DRV5056 Output Voltage
          3. 2.3.1.2.3 DRV5056 Placement
        3. 2.3.1.3 Power Supply
        4. 2.3.1.4 Transistor Circuit for Creating High-Voltage Enable Signal
      2. 2.3.2 Alternative Implementations
        1. 2.3.2.1 Replacing 20-Hz Tamper Switches With 5-Hz Tamper Switches
        2. 2.3.2.2 Using Shielding to Replace Tamper Switches and Stray Field Switch
        3. 2.3.2.3 Replacing Hall-Based Wake-Up Alert Function With a Mechanical Switch
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Installation and Demonstration Instructions
      2. 3.1.2 Test Points and LEDs
      3. 3.1.3 Configuration Options
        1. 3.1.3.1 Disabling Hall-Effect Switches
        2. 3.1.3.2 Configuring Hardware for Standalone Mode or Connection to External Systems
    2. 3.2 Test Setup
      1. 3.2.1 Output Voltage Accuracy Testing
      2. 3.2.2 Magnetic Tampering Testing
      3. 3.2.3 Current Consumption Testing
    3. 3.3 Test Results
      1. 3.3.1 Output Voltage Accuracy Pre-Calibration Results
      2. 3.3.2 Output Voltage Accuracy Post-Calibration Results
      3. 3.3.3 Magnetic Tampering Results
      4. 3.3.4 Current Consumption Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 サポート・リソース
    5. 4.5 Trademarks
2.3.1.2.1 DRV5056 Power

The DRV5056 can consume up to 10 mA, which would drain the battery if the DRV5056 was constantly powered. To reduce current consumption, the DRV5056 is powered through the TPS22917 load switch. The TPS22917 takes one of the system wake-up signals as an input. If the wake-up signal indicates that the system should be in active mode, the TPS22917 connects the VCC rail on the board to the VCC pin of the DRV5056. If the wake-up signal indicates that the system should be in sleep mode, the TPS22917 disconnects the VCC rail from the DRV5056 device, thereby preventing the DRV5056 from draining the battery when the trigger is not pressed. The LPWR D5 LED on the board indicates whether the DRV5056 is powered by turning ON when the DRV5056 is powered (active mode) and turning OFF when the DRV5056 is not powered (sleep mode).

Since the TPS22917 expects the wake-up signal to be active high but an active low signal is produced by the SN74HCS00, a SN74AUP1G00 NAND gate is used to convert the active low wake-up signal to an active high wake-up signal. Although the TPS22917 is used in this design, the board can be redesigned to replace both the active-high TPS22917 and SN74AUP1G00 with only one active-low TPS22916.

If desired, the board can also be modified to not be powered through the TPS22917 by removing R22. If R22 is removed, the DRV5056 can be powered from an external rail applied at the VCC_2 test point.