From the schematic diagram, op amp U1, a THS3491 current feedback amplifier, is the signal path amplifier which will drive up to 50 Vpp output based on the input signal provided by signal source VG1. This amplifier is configured in a non-inverting gain of 10 V/V. This closed-loop gain is established from the simple relationship Av = 1 + (R2 / R1). Of course, 50 Vpp exceeds the THS3491 recommended maximum supply rating of 32 V, as well as the absolute maximum (fault condition) supply rating of 33 V. Note that these ratings apply to the differential voltage across the supply pins and not the absolute magnitude relative to ground.

Hence, the role of the other two THS3491 op amps U2 and U3, is to track the output of U1 and shift its supply voltages up and down alongside the output voltage. This technique allows a wider output swing, while keeping the supply rails safe within the recommended differential rating at all times.

Vs+ and Vs– are the two main power supplies of the board, and are recommended to operate at +32 V and –32 V, respectively. Figure 2-2 shows how THS3491 op amps U2 and U3 are connected to either Vs+ or Vs– and ground in a single-supply configuration. Vcc and Vee are used to designate the bootstrapped power supply pins of the signal amplifier (U1), as these supplies are variable with respect to the output voltage swing.

The output pins of U2 and U3 actively drive the Vcc and Vee supply pins of U1, supplying its quiescent current, as well as the current delivered to its load. U2 and U3 are both connected as voltage followers with a gain of 1 V/V. The input voltages of U2 and U3 are determined by the varying output voltage of U1, resistive voltage dividers R6, R7 and R8, R9, and the supply pins Vs– and Vs+ respectively. The voltage dividers are connected between the main supply pins and the output, such that the inputs to the supply modulating amplifiers (VinU2, VinU3) can be derived from following equations:

These same equations are used to determine the U1 supply voltages at any time, as U2 and U3 are configured as non-inverting buffers to drive the power supplies of U1 as shown in Equation 3 and Equation 4.

In practice, the values derived from Equation 1 through Equation 4 will differ slightly due to the tolerance of resistors making up the voltage divider, and the THS3491 offset voltage. The difference is relatively small as 1% resistors are used and the typical offset voltage is only 1 mV, so for simplicity these errors are not considered. Additionally, The THS3491 has a high power-supply rejection ratio (PSRR) of about 80 dB, which helps minimize output referred voltage offset changes as the supply voltages of U1 follow its output voltage.

Figure 2-2 shows the DC voltages occurring at various nodes in the design. The Vs+ and Vs– supplies are set to ±32 V respectively, and the input applied to U1 is 0 V, in this case. The output of U1 is nearly 0 V, deviating by the output referred voltage offset (Voso) generated by U1 in a gain of 10 V/V. The difference between the respective Vs+ and Vs– power supplies and the 0-V output, divided by 2 via the resistive dividers, establishes VinU2 as 16 V and Vin U3 as –16 V. From the buffer configuration, the output of U2 is 16 V and the output of U3 is –16 V, a difference of +32 V between them. That is the voltage that appears across the supply pins of U1 (Vcc – Vee).

Figure 2-3 shows the circuit again with a positive input voltage applied to U1. This corresponds to the circuit behavior during the positive half-cycle of a sinusoid or square wave. In this case, 2 V is applied at the input of U1, resulting in 20 V at the output, due to the gain configuration of +10 V/V. This increases the input voltages of U2 and U3 as defined by Equation 1 and Equation 2, respectively. Inserting the previoulsy-described values, these equations yield an input of 26 V at U2 and –6 V at U3. Extending these results to Equation 3 and Equation 4, it is apparent that amplifier U1 is operating with unparallel supply voltages of +26 V and –6 V, as both supplies are shifted upward by exactly half of the increase in output voltage. Note that the differential voltage across the U1 supply pins remains the same at 32 V, which is consistent with the recommended operating conditions in the data sheet.

This example is shown again in Figure 2-4 with a negative input voltage applied to U1, which corresponds to the negative half-cycle of a sinusoid or square wave. In this case, –2 V is applied at the input of U1, resulting in –20 V at the output. This decreases the input voltages of U2 and U3 as defined by Equation 1 and Equation 2, resulting in an input of 6 V at U2 and –26 V at U3. Extending these results to Equation 3 and Equation 4, now amplifier U1 is operating with unparallel supply voltages of +6 V and –26 V, as both supplies are shifted down by exactly half of the decrease in output voltage. As in the previous case, the differential voltage across the U1 supply pins remains a consistent 32 V.

Figure 2-5 shows the voltage swing for the output and power supply nodes across the common-mode input range of the circuit. The maximum voltage output swing is defined by the input common mode headroom of the supply modulating amplifiers, and the output voltage headroom of the driver amplifier. In theory, this design could produce a reliable output as high as 52-Vpp over process, however this document will focus on 50-Vpp output as this is the design target (Table 1-1).

Figure 2-6 presents this data again in the time domain with a 1-MHz sinusoidal output. This data was generated with the TINASpice simulation tool and shows how supply rails Vcc and Vee track around the output voltage swing.