JAJU854 September   2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specification
      1. 1.1.1 Intel® Stratix® 10 Power Tree Example
      2. 1.1.2 Intel® Agilex™ Power Tree Example
      3. 1.1.3 Xilinx Versal™ Power Tree Example
      4. 1.1.4 Xilinx Virtex-7® Power Tree Example
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS53688
      2. 2.3.2 TPS650861
      3. 2.3.3 TPSM5D1806
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
      1. 3.2.1 TPS53688 Programming Setup
      2. 3.2.2 TPS53688 Transient Test Setup
      3. 3.2.3 TPS650861 Programming Setup
      4. 3.2.4 TPS650861 and TPSM5D1806 Transient Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Efficiency Results
      2. 3.3.2 Transient Results
        1. 3.3.2.1 TPS53688 Transient Results
        2. 3.3.2.2 TPS650861 Transient Results
        3. 3.3.2.3 TPSM5D1806 Transient Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 サポート・リソース
    5. 4.5 Trademarks
  10. 5About the Author

3.2.3 TPS650861 Programming Setup

Figure 3-3 TPS650861 USB2ANY Setup

The TPS650861 requires a USB2ANY and the IPG-UI GUI to interface, and modify the TPS650861 voltage outputs and sequencing. For more information on how to use the IPG-UI GUI and how to program the TPS650862 see the TPS65086100 Non-Volatile Memory Programming Guide.