JAJU857 December 2022
In place of 0 Ω R23, a DC offset circuit was used. The auto-oscillation duty cycle was found to be 50.10% at steady state with no fault condition. For the best case, the duty cycle is 50.00% with no fault condition. This duty-cycle shift resulted in a consistent 200-mV DC offset evident on the final output of the filter stage. The DC offset is an issue,because thresholds for positive and negative fault current are not the same. By zeroing the AC_SENSING output, both negative and positive ground fault current have the same threshold. This offset is due to the magnetic core and can vary depending on material used.
Figure 3-10 shows the schematic for the dual-supply, inverting amplifier circuit configuration.
The inverting op-amp configuration takes an input signal that is applied directly to the inverting input terminal and outputs a signal that is the opposite polarity as the input signal. The benefit of this topology is that the topology avoids common-mode limitations. The load resistance for this topology is equal to R2. The values of the resistors in the feedback network determine the amount of gain to amplify the input signal.
Equation 4 displays the transfer function for the dual-supply, inverting amplifier circuit configuration with level shifting input shown in Figure 3-10.
Capacitor C2 filters noise that can be introduced from the VREF input. Equation 5 calculates the cutoff frequency due to C2.
Capacitor C4 provides the option to filter the output. The cutoff frequency of the filter can be calculated using Equation 6.