JAJU857 December   2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 System Design Theory
      1. 2.2.1 Detection Principals
      2. 2.2.2 Saturation
      3. 2.2.3 General Mode of Operation
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8220
      2. 2.3.2 OPAx202
      3. 2.3.3 TLVx172
      4. 2.3.4 TLV7011
      5. 2.3.5 INA293
      6. 2.3.6 SN74LVC1G74
      7. 2.3.7 TLV767
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1  Board Overview
      2. 3.1.2  Filter Stage
      3. 3.1.3  Differential to Single-Ended Converter
      4. 3.1.4  Low-Pass Filter
      5. 3.1.5  Full-Wave Rectifier
      6. 3.1.6  DC Offset Circuit
      7. 3.1.7  Auto-Oscillation Circuit
        1.       31
      8. 3.1.8  DRV8220 H-Bridge
      9. 3.1.9  Saturation Detection Circuit
      10. 3.1.10 H-Bridge Controlled by DFF
      11. 3.1.11 MCU Selection
      12. 3.1.12 Move Away From Timer Capture
      13. 3.1.13 Differentiating DC and AC From the Same Signal
      14. 3.1.14 Fluxgate Sensor
    2. 3.2 Software Requirements
      1. 3.2.1 Software Description for Fault Detection
    3. 3.3 Test Setup
      1. 3.3.1 Ground-Fault Simulation
    4. 3.4 Test Results
      1. 3.4.1 Linearity Over Temperature
    5. 3.5 Fault Response Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

2.3.6 SN74LVC1G74

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when powered down.