JAJU871 December   2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Theory of Operation
    4. 2.4 Highlighted Products
      1. 2.4.1 TPS7A57 Low Dropout (LDO) Regulator
      2. 2.4.2 LMG1020 Low Side Driver
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
      1. 3.2.1 Optional Load Transient Circuit Operation
    3. 3.3 Test Results
      1. 3.3.1 Current Sharing
      2. 3.3.2 VLOAD vs ILOAD
      3. 3.3.3 Load Transient Response
      4. 3.3.4 Current Limit
      5. 3.3.5 Startup
      6. 3.3.6 Noise
      7. 3.3.7 PSRR
      8. 3.3.8 Thermal
      9. 3.3.9 Thermal Limit Protection
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 サポート・リソース
    5. 4.5 Trademarks
  10. 5About the Author

3.2.1 Optional Load Transient Circuit Operation

The TPS7A57EVM-081 reference design contains an optional high-performance load transient circuit to allow efficient testing of the parallel TPS7A57 LDO's load transient performance. To use the optional load transient circuit, install the correct components in accordance with the application. Modify the input and output capacitance connected to the parallel TPS7A57 LDO's to match the expected operating conditions. Determine the desired peak current to test, and modify the parallel resistor combination of R13, R14, R15, R16, and R17 as shown:

Equation 5. I P e a k = V O U T R 13 R 14 R 15 R 16 R 17

The slew rate of the load step can be adjusted by C19, R18, R19, and R20. In this section, only R19 and R20 are adjusted to set the slew rate. For a 0-mA to 13.5-A to 0-mA load step, use Table 3-1 to select a value of R19 and R20 that results in the desired rise or fall time.

Table 3-1 Suggested Ramp Rate Resistor Values
R19 R20 Rise, Fall Time
20 kΩ 32.4 kΩ 16.9 µs
15.8 kΩ 25.5 kΩ 13.5 µs
10 kΩ 16.2 kΩ 8.45 µs
4.99 kΩ 8.45 kΩ 4.25 µs
1.5 kΩ 2.61 kΩ 1.35 µs

After the EVM is modified (if needed), connect a power supply to banana connectors J21 (VDD) and J25 (GND) with a 5-V DC supply and a 1-A DC current limit. As illustrated in Section 3.3.3, the parallel TPS7A57 reference design transient response is very fast and the output voltage recovers in well under 1 ms after the initial load transient. Use a pulse-duration limit of 1 ms to prevent excessive heating of the pulsed resistors (R13, R14, R15, R16, and R17). Configure a function generator for the 50-Ω output, in a 0-V DC to 5-V DC square pulse. If necessary, burst mode can be configured in the function generator for repetitive, low duty cycle, load transient testing.

A 20-kΩ resistor is installed on the EVM at R19, and a 20-kΩ resistor is installed on the EVM at R20. These resistors provide approximately 0.75-A/μs slew rate from 0 mA to 13.5 A, and 1.3-A/μs slew rate from 13.5 A to 0 mA.