Based on the key system specification, the maximum solenoid load is 1.7 A. The boost-buck DC-DC power stage, consisting of LM5122 and LMR33630, is designed to support 2 A of continuous load. Note, WEBENCH® Power Designer was used to help design the power stage. The key design calculations for the LM5122 Boost Stage are shown below. For more details on design considerations, please refer to the device data sheet.

Timing Resistor RT (R53)

The boost switching frequency of 250 kHz was selected as a good compromised between size and efficiency. The RT resistor is calculated as follows:

A standard value of 36.5 kΩ was selected for RT.

UVLO Divider RUV2 (R43), RUV1 (R47)

The desired startup voltage and the hysteresis are set by the voltage divider RUV2, RUV1. The UVLO shutdown voltage should be high enough to enhance the low-side N-channel MOSFET switch fully. For this design, the startup voltage was set to 5.5 V, which is 0.5 V below the minimum input voltage. VHYS was set to 0.5 V. This resulted in an input-voltage shutdown threshold of 5 V. The values of RUV2, RUV1 are calculated as follows:

49.9 kΩ and 14 kΩ were selected for RUV2 and RUV1, respectively.

Input Inductor LIN (L2)

The first step is to calculate the maximum duty cycle and maximum input current. Assuming an efficiency of 0.9:

The inductor ripple current is typically set between 20% and 40% of the full load current, known as a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. In addition, a higher ripple may require a higher inductor saturation rating. For this example, a high ripple ratio (RR) of 0.6, 60% of the input current was chosen to minimize inductor size. Knowing the switching frequency and the typical input voltage, the inductor value can be calculated as follows:

The closest standard value of 4.7 μH (XAL6060-472ME) was chosen for L_in (i.e. L2) for this design. Alternatively, if a ripple ratio of 0.3 is desired, a 10 μF (XAL6060-103ME) could be chosen.

The saturation current rating of inductor should be greater than the peak inductor current, which is calculated at the minimum input voltage and full load:

To account for tolerances (i.e. inductor, frequency, voltage) a 25% margin is added to the result. The Ipeak = 6.7A × 1.25 = 8.4 A (worst-case). The chosen inductor (XAL6060-472ME) saturation current rating is 10.5 A.

Note, I_RMS is approximately I_IN given a small RR value:

Inductor wire loss is calculated as follows:

Note: for higher power applications (i.e. higher flux density), inductor core losses may be significant.

Current Sense Resistor RS (R40)

The maximum peak input current capability should be 20% to 50% higher than the required peak current at low input voltage and full load, accounting for tolerances (that is, V_CS-TH1, peak current). For this design, a 40% margin was selected.

8 mΩ was selected for Rs. The maximum power loss of Rs is calculated as follows:

To account for the sense resistor temperature derating and tolerance, a minimum power rating of 1 W is required. For this design, the chosen Rs (PMR100HZPFU8L00) is rated for 2 W.

Current Sense Filter RCSFP (R45), RCSFN (R46), CCS (C58)

The current sense filter is optional. Based on the data sheet recommendations, 100 pF for CCS and 100 Ω for RCSFP, RCSFN were chosen.

Slope Compensation Resistor RSLOPE

For duty cycles greater than 50%, peak current mode regulators are subject to sub-harmonic oscillation. In this design the maximum duty cycle is about 57% when V_in is 6 V. Subharmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. This subharmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope compensation, to the sensed inductor current.

The K value was selected to be 0.6 at the minimum input voltage. R_slope should be carefully selected so that the sum of sensed inductor current and slope compensation is less than COMP output high voltage. In any case, K should be greater than at least 0.5. At higher switching frequency over 500 kHz, K factor is recommended to be greater than or equal to 1 because the minimum on-time affects the amount of slope compensation due to internal delays.

For this design, 140 kΩ was selected for R_slope.

Output Capacitor COUT

The output voltage ripple is dominated by ESR of the output capacitors. Paralleling output capacitor is a good choice to minimize effective ESR and split the output ripple current into capacitors. In this design, one 180-µF bulk aluminum capacitor (EEE-FK1H181SP) and three 10-µF ceramic capacitors (UMK316BBJ106KL-T) were used to share the output ripple current and source the required charge. Assuming an effective 50 mΩ ESR for the hybrid output capacitor network, the output voltage peak-peak ripple at the minimum input voltage is calculated as follows:

The calculated output ripple voltage is 2% of the output voltage, which is dominated by the effective output ESR. Adding a 25% margin to account for tolerances, the worst-case output voltage ripple is 2.5%.

The output cap RMS current is:

Input Capacitor CIN

The input capacitors smooth the input voltage ripple. In this design, two 330 µF bulk aluminum capacitors (EMVA500ATR331MKE0S), five 10-µF ceramic capacitors (CL31B106KBHNNNE), and one 1-µF ceramic capacitor (UMK107AB7105KA-T) were used. The maximum input voltage peak-peak ripple which happens when the input voltage is half of the output voltage can be calculated as follows:

The input cap RMS current is:

Bootstrap Capacitor CBST (C64) and Boost Diode DBST (D3)

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side N-channel MOSFET device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. C_BST must be a good-quality, low-ESR, ceramic capacitor located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap capacitor is calculated as follows:

where

• Q_g is the high-side N-channel MOSFET gate charge

• ΔV_BST is the tolerable voltage droop on CBST, which is typically less than 5% of VCC or 0.15 V, conservatively

The chosen CSD18543Q3A MOSFET has 10 nC at 10 V, which means the C_{BST_min} is only 66.7 nF:

In this design, a 0.1-μF ceramic capacitor (C1005X5R1H104K050BB) was used based on the data sheet recommended value.

The voltage rating of DBST must be greater than the peak SW node voltage plus 16 V. The maximum switch node voltage is approximately the output voltage plus some ringing. Thus a minimum diode voltage rating including the 16 V margin is 30 V. A low leakage diode is mandatory for the bypass operation. The leakage current of DBST must be low enough for the BST charge pump to maintain a sufficient high-side driver supply voltage at high temperature. For this design, a 100-V, 1-A Schottky diode (MBR1H100SFT3G) was chosen.

VCC Capacitor CVCC

The primary purpose of the VCC capacitor is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The value of CVCC must be at least 10 times greater than the value of CBST (i.e. 1 μF) and should be a good-quality, low-ESR, ceramic capacitor. Also, to account for voltage derating, the voltage rating should be at least 2 times the VCC voltage. In this design, a 10-μF, 16-V ceramic capacitor (EMK107BBJ106MA-T) was used.

Output Voltage Divider RFB1 (R44), RFB2 (R48)

RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as follows:

The ratio between R_COMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a corresponding larger value for R_COMP. RFB2 should be large enough to keep the total divider power dissipation small. In this design, 39.9 kΩ and 3.65 kΩ were chosen for RFB2 and RFB1, respectively (i.e. Vout = 14.3 V).

Soft-Start Capacitor CSS (C65)

The soft-start time (t_SS) is the time for the output voltage to reach the target voltage from the input voltage. The soft-start time is not only proportional with the soft-start capacitor, but also depends on the input voltage. With 0.1 µF of CSS, the soft-start time is calculated as follows:

Restart Capacitor CRES (C66)

The restart capacitor determines restart delay time t_RD and hiccup mode off time t_RES. t_RD must be greater than t_SS(MAX). The minimum required value of C_RES can be calculated at the low input voltage as follows:

A standard value of 0.33 µF was selected for C_RES (i.e. t_RD = 13.2 ms).

Low-Side Power Switch Q

Selection of the power N-channel MOSFET devices by breaking down the losses is one way to compare the relative efficiencies of different devices. Losses in the low-side N-channel MOSFET device can be separated into conduction loss, switching loss, and gate charge loss. Low-side conduction loss of CSD18543Q3A is approximately calculated as follows:

Where, D is the duty cycle and the factor of 1.5 accounts for the increase in the N-channel MOSFET device on-resistance due to heating. The R_DS(ON) used here is based on a conservative estimate (V_gs = 4.5 V) since the actual V_gs drive is about 6 V.

Switching loss occurs during the brief transition period as the low-side N-channel MOSFET device turns on and off. During the transition period both current and voltage are present in the channel of the N-channel MOSFET device. The low-side switching loss is approximately calculated as follows:

t_R and t_F are the switching times (including the rise and fall times) corresponding to the rise and fall transitions. During these times switching loss occurs for the low-side N-channel MOSFET device. They are calculated as follows:

MOSFET gate losses are caused by the energy required to charge the MOSFET gate. That is, the total Q_g at the gate voltage of the circuit. These are both turn-on and turn-off gate losses. The power dissipation is approximately split between the gate driver and the MOSFET:

Note, the temperature factor assumption can be verified afterwards by determining the junction temperature from the total power dissipation calculations. The R_DS(ON) of the MOSFET versus temperature is shown in the data sheet:

From the data sheet, the normalized on-state resistance for CSD18543Q3A (V_gs = 4.5 V) is well under 1.2 at this junction temperature so our initial assumption of 1.5 is still valid. Note, the case temperature is very close to the junction temperature since R_θJC = 1.9 ^oC/W.

An alternative design approach is to start with the target FET junction temperature, working back to the maximum R_DS(ON), and then cross check with the data sheet R_DS(ON) at that temperature.

High-Side Power Switch QH and Additional Parallel Schottky Diode

Losses in the high-side N-channel MOSFET device can be separated into conduction loss, dead-time loss, reverse recovery loss, and gate charge loss. Switching loss is calculated for the low-side N-channel MOSFET device only. Switching loss in the high-side N-channel MOSFET device is negligible because the body diode of the high-side N-channel MOSFET device turns on before and after the high-side N-channel MOSFET device switches (i.e. zero voltage switching).

High-side conduction loss is approximately calculated as follows:

Dead-time loss is approximately calculated as follows:

where

• V_D is the forward voltage drop of the high-side NMOS body diode.

• t_DLH and t_DHL are the low to high and high to low dead time delays, respectively.

Reverse recovery characteristics of the high-side N-channel MOSFET switch strongly affect efficiency, especially when the output voltage is high. Small reverse recovery charge helps to increase the efficiency while also minimizes switching noise. Reverse recovery loss is calculated as follows:

Gate charge loss is calculated as follows:

Note, an additional Schottky diode can be placed in parallel with the high-side switch to improve efficiency. Usually, the power rating of this parallel Schottky diode can be less than the high-side switch’s because the diode conducts only during dead-times. The power rating of the parallel diode should be equivalent or higher than high-side switch’s if bypass operation is required, hiccup mode operation is required or any load exists before switching.

Bias Losses

An additional source of power loss includes bias losses. The total bias current budget is about 10 mA. With a 6 V input, the loss is 60 mW from biasing.

Snubber Components

A resistor-capacitor snubber network across the high-side N-channel MOSFET device reduces ringing and spikes at the switching node. Selecting the values for the snubber is best accomplished through empirical methods. A 470-pF capacitor and 8.2-Ω resistor were chosen as placeholders in this design.

Loop Compensation Components CCOMP, RCOMP, CHF

R_COMP, C_COMP and C_HF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the following four steps:

1. Select:

Select the cross over frequency (f_cross) at one fourth of the RHP zero or one tenth of the switching frequency, whichever is lower. RHP zero at minimum input voltage should be considered if the input voltage range is wide.

In this design, a 5 kHz crossover frequency was used instead of 11 kHz for added margin.

Note, the size of the output capacitor plays a significant role in how wide the loop bandwidth is (Reference SLVA452). Once the minimum capacitance is met, meeting the output ripple specification, the following equation is used to estimate the output capacitance needed to meet the application's load transient requirement for the maximum voltage dip (V_TRAN) after a given load step (ΔI_TRAN). V_TRAN is 2.5% of output voltage and ΔI_TRAN is 2 A:

2. Determine required R_COMP to set crossover.

Knowing f_cross, R_COMP is calculated as follows:

In this design, 23.2 kΩ was selected for R_COMP.

3. Determine C_COMP to cancel load pole.

Place error amplifier zero at the twice of load pole frequency. For boost converters with ceramic capacitor(s) in parallel with a much larger, high-ESR capacitor, use the total capacitance in parallel for C_out for this step (Reference SLVA452). Knowing R_COMP, C_COMP is calculated as follows:

A standard value of 15 nF is recommended.

4. Determine C_HF to cancel ESR zero.

For boost converters with ceramic capacitor(s) in parallel with a much larger, high-ESR capacitor, only use the high-ESR capacitor's capacitance and ESR for this step (Reference SLVA452). Knowing R_COMP, RESR and C_COMP, C_HF is calculated as follows:

A standard value of 2.7 nF is recommended.

Alternatively, if a lower ESR bulk capacitor were used the f_{Z_ESR} can be moved beyond the f_cross.

Bypass Operation (VOUT = VIN)

MODE pin is tied to 3.3 V to enable Forced-PWM (FPWM). Forced-PWM mode is the recommended PWM configuration when bypass operation is required.