JAJU878
November 2022
ADS117L11
,
ADS127L11
概要
リソース
特長
アプリケーション
5
1
System Description
1.1
Key System Specification
2
System Overview
2.1
Block Diagram
2.2
Design Considerations
2.2.1
Signal-Chain Voltage Levels
12
2.2.2
ADC Configuration
2.2.3
ADC Clocking and Synchronization
2.2.4
Differential Low-Pass Filter
2.2.5
Current Source
2.2.6
Gain Stage and High-Pass Filter
2.3
Highlighted Products
2.3.1
ADS127L11
2.3.2
THS4551
3
System Design Theory
3.1
IEPE Sensor
3.1.1
IEPE Sensor Parameters
3.1.1.1
Sensitivity and Measurement Range
3.1.1.2
Excitation, Output Bias Voltage, and Output Impedance
3.1.1.3
Linearity and Temperature Variance
3.1.1.4
Frequency Response
3.1.1.5
Noise and Dynamic Range
4
Hardware, Software, Testing, and Test Results
4.1
Hardware Description
4.1.1
Board Interface
4.1.2
Power Configuration
4.1.2.1
Power Sequence
4.1.2.2
Analog Supply
4.1.2.3
Digital Supply
4.1.2.4
Excitation Current Supply
4.1.2.5
SPI Connectivity Modes and Their Assembly Variants
4.1.2.5.1
Daisy-Chain Mode
4.1.2.5.2
Parallel SDO Mode
4.1.2.5.3
Parallel SDI Mode and Parallel SDO Mode
4.1.2.5.4
Clocking Modes
4.2
Software Requirements
4.3
Test Setup and Procedure
4.3.1
Noise Floor and SNR
4.3.2
Gain and Input Range
4.3.3
Crosstalk
4.3.4
Total Harmonic Distortion
4.3.5
Clock Image Rejection
4.3.6
Synchronization of the ADCs
4.3.7
Fault Detection Circuit
4.4
Test Results
4.4.1
Noise Floor and Dynamic Range
4.4.2
Gain and Input Range
4.4.3
Crosstalk
4.4.4
Total Harmonic Distortion
4.4.5
Clock Image Rejection
4.4.6
Synchronization of the ADCs
4.4.7
Fault Detection Circuit
4.4.8
Test With Actual IEPE Sensor
4.4.9
Measurement Results Summary
5
Design and Documentation Support
5.1
Design Files
5.1.1
Schematics
5.1.2
BOM
5.2
Software
5.3
Documentation Support
5.4
サポート・リソース
5.5
Trademarks
6
About the Author
5
Design and Documentation Support