JAJU878 November   2022 ADS117L11 , ADS127L11

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specification
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Signal-Chain Voltage Levels
        1.       12
      2. 2.2.2 ADC Configuration
      3. 2.2.3 ADC Clocking and Synchronization
      4. 2.2.4 Differential Low-Pass Filter
      5. 2.2.5 Current Source
      6. 2.2.6 Gain Stage and High-Pass Filter
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L11
      2. 2.3.2 THS4551
  8. 3System Design Theory
    1. 3.1 IEPE Sensor
      1. 3.1.1 IEPE Sensor Parameters
        1. 3.1.1.1 Sensitivity and Measurement Range
        2. 3.1.1.2 Excitation, Output Bias Voltage, and Output Impedance
        3. 3.1.1.3 Linearity and Temperature Variance
        4. 3.1.1.4 Frequency Response
        5. 3.1.1.5 Noise and Dynamic Range
  9. 4Hardware, Software, Testing, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 Board Interface
      2. 4.1.2 Power Configuration
        1. 4.1.2.1 Power Sequence
        2. 4.1.2.2 Analog Supply
        3. 4.1.2.3 Digital Supply
        4. 4.1.2.4 Excitation Current Supply
        5. 4.1.2.5 SPI Connectivity Modes and Their Assembly Variants
          1. 4.1.2.5.1 Daisy-Chain Mode
          2. 4.1.2.5.2 Parallel SDO Mode
          3. 4.1.2.5.3 Parallel SDI Mode and Parallel SDO Mode
          4. 4.1.2.5.4 Clocking Modes
    2. 4.2 Software Requirements
    3. 4.3 Test Setup and Procedure
      1. 4.3.1 Noise Floor and SNR
      2. 4.3.2 Gain and Input Range
      3. 4.3.3 Crosstalk
      4. 4.3.4 Total Harmonic Distortion
      5. 4.3.5 Clock Image Rejection
      6. 4.3.6 Synchronization of the ADCs
      7. 4.3.7 Fault Detection Circuit
    4. 4.4 Test Results
      1. 4.4.1 Noise Floor and Dynamic Range
      2. 4.4.2 Gain and Input Range
      3. 4.4.3 Crosstalk
      4. 4.4.4 Total Harmonic Distortion
      5. 4.4.5 Clock Image Rejection
      6. 4.4.6 Synchronization of the ADCs
      7. 4.4.7 Fault Detection Circuit
      8. 4.4.8 Test With Actual IEPE Sensor
      9. 4.4.9 Measurement Results Summary
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Software
    3. 5.3 Documentation Support
    4. 5.4 サポート・リソース
    5. 5.5 Trademarks
  11. 6About the Author

2.2.2 ADC Configuration

As mentioned in the previous section, a 4-V reference is to be used with the ADS127L11 to maximize the dynamic range. A 16-MHz oscillator clock is also selected as clock reference to the ADC as well as an SPI clock. The ADC can run with clocks up to 25 MHz.

To get the best performance out of the signal-chain, the ADS127L11 ADC has to be configured properly. The following list shows the required settings:

  • Data Width (resolution) = 24 bits
  • Speed Mode= High Speed
  • Filter Type= Wide Bandwidth
  • INP_RNG= VREF
  • REF_RNG= High-reference range
  • VCM=Enabled
  • AINP_BUF, AINN_BUF=Enabled
  • CLK_SEL=External

The ADC can be used either in daisy chain or in parallel SDO modes. Equation 1 shows the maximum data rate for daisy-chain mode.

Equation 1. Maximum data rate = SPI Clk / (devices in the chain × bit per frame)

For a 16-MHz SPI clock, 4 devices, and 32b per frame, the maximum data rate is 125 kSPS. To get the output data rate to 125 kSPS, set the OSR=64.

For parallel SDO mode and using the wideband filter, the data rate can be set to a maximum of 400 kSPS. With a 16-MHz clock, only OSR = 64 is possible, and that gives an output data rate of 250 kSPS. To achieve 400 kSPS, replace the onboard 16-MHz oscillator with a 25-MHz oscillator.

For more details about the daisy-chain and parallel connections, see the ADS127L11 400-kSPS, Wide-Bandwidth, 24-Bit, Delta-Sigma ADC data sheet and ADS127L11 in Simultaneous-Sampling Systems application brief.