To make sure proper synchronization is maintained between the four ADCs:
- Monitor the four nDRDY signals on J7
- In a good test case, those nDRDYx signals have the exact time for high-to-low transition. Record the delay between those signals using the 4-channel scope.
- Use persistent waveform display to capture variance of nDRDY delay between different channels (use one of the nDRDY signals as trigger)
- Repeat the previous test for each new SPI SCLK frequency and for both daisy and parallel SPI modes