JAJU881 December   2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 Devices
        1. 2.3.1.1 AWR2243
        2. 2.3.1.2 AM2732R
        3. 2.3.1.3 LP876242-Q1
        4. 2.3.1.4 LM62460-Q1
        5. 2.3.1.5 TCAN1043A-Q1
        6. 2.3.1.6 TCAN1044A-Q1
        7. 2.3.1.7 DP83TC812-Q1
        8. 2.3.1.8 TPS61379-Q1
        9. 2.3.1.9 TMP102-Q1
  8. 3System Design Theory
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
      1. 4.2.1 Virtual Antenna Array
    3. 4.3 Test Results
      1. 4.3.1 Angle Resolution Measurement
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 20 GHz (FMCW) RF LO Sync
        2. 5.1.3.2 PCB Layer Stackup
        3. 5.1.3.3 Board Photos
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 サポート・リソース
    5. 5.5 Trademarks

2.3.1.7 DP83TC812-Q1

The DP83TC812-Q1 device is an IEEE 802.3bwcompliant automotive PHYTER™ Ethernet physical layer transceiver which can work with Unshielded Twisted Pair cable. The PHY supports TC10 sleep and wake features. It provides all physical layer functions needed to transmit and receive data over unshielded single twisted-pair cables. The device provides xMII flexibility with support for standard MII, RMII, RGMII, and SGMII MAC interfaces. The PHY also integrates a low pass filter on the MDI side to reduce emissions.

This device includes the Diagnostic Tool Kit, providing an extensive list of real-time monitoring tools, debug tools and test modes. Within the tool kit is the first integrated electrostatic discharge (ESD) monitoring tool. It is capable of counting ESD events on MDI as well as providing real-time monitoring through the use of a programmable interrupt. Additionally, the DP83TC812-Q1 includes a pseudo random binary sequence (PRBS) frame generation tool, which is fully compatible with internal loopbacks, to transmit and receive data without the use of a MAC. The device is housed in a 6.00-mm × 6.00-mm, 36-pin VQFN wettable flank package. This device is pin-2- pin compatible with DP83TG720 (1000BASE-T1). It is also form factor compatible with DP83TC811. This would allow for a single PCB layout to be used for DP83TC811, DP83TC812, DP83TC814, and DP83TG720.