The TPS82130 has a built-in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG pin is an open-drain output that requires a pullup resistor. Because V_OUT is the IC ground in this configuration, the PG pin is referenced to V_OUT instead of ground, which means that the TPS82130 device pulls PG to V_OUT when it is low.

This behavior can cause difficulties in reading the state of the PG pin, because in some applications the IC detecting the voltage level of the PG pin may not be able to withstand negative voltages. The level-shifter circuit shown in Figure 1-7 removes any difficulties associated with the offset PG pin voltages by eliminating the negative output signals of the PG pin. If the PG pin functionality is not required, it may be left floating or connected to V_OUT without this circuit. Note that to avoid violating its absolute maximum rating, the PG pin should not be driven more than 6 V above the negative output voltage (IC ground).

Figure 1-7 PG Pin Level Shifter

Inside the TPS82130, the PG pin is connected to an N-channel MOSFET (Q3). By tying the PG pin to the gate of Q1, when the PG pin is pulled low, Q1 is off and Q2 is on because Q2's V_GS is at V_CC. SYS_PG is then pulled to ground.

When Q3 turns OFF, the gate of Q1 is pulled to ground potential which turns Q1 ON. This sequence of events pulls the gate of Q2 below ground, which turns it OFF. SYS_PG is then pulled up to the V_CC voltage. Note that the V_CC voltage must be at an appropriate logic level for the circuitry connected to the SYS_PG net.

Figure 3-19 and Figure 3-20 show this PG pin level-shifter sequence. The PG signal activates the PG pin level-shifter circuit and the G/D node signal represents the shared node between Q1 and Q2. This circuit has been tested with a V_CC of 5 V and dual NFET Si1902DL. The SYS_PG net is the output of the circuit and goes between ground and 5 V and is easily read by a separate device.