Design Description

This circuit document describes how to translate a high-voltage signal (for example, ±10V) to a low voltage ADC input (for example, 0V to 5V). This circuit does not require any high-voltage supply to operate, but rather uses a voltage divider and level shift to translate the input signal. This circuit shows the OPA320 op amp and ADS8860 SAR ADC, but the topology applies to many different ADCs. This design can be used in a wide range of applications where a high-voltage input needs to be translated such as analog input modules for PLCs, analytical lab instrumentation, and factory automation and control.

Specifications

Design Notes

1. Select a C0G type capacitor for Cfilt to minimize distortion.
2. Use 0.1% 20ppm/°C film resistors or better to minimize gain error and drift.
3. The input impedance of this circuit is R_in = R_a + R_b||R_c. For a high-impedance input, use a high-voltage amplifier buffer (for example, Vcc = +15V and Vee = –15V). Alternatively, increase the input impedance by multiplying R_a, R_b, and R_c by the same factor. However, increasing the resistance on all the resistors impacts the system noise.

Component Selection

1. The first step is to select the amplifier input and output range. In this example, the input range is –10V to +10V. The amplifier output range is set according to the ADC input and the amplifier linear output range. The ADC input range in this example is set by the reference voltage and is 5V. The amplifier supply is set to 5V to match the ADC input range. The output of the amplifier cannot swing to the power supply rails because of output swing limitations (that is, linear range for OPA320 0.1V < V_OUT < 4.9V). For this example, an output swing of 0.2V to 4.8V is selected for the input signal of –10V to 10V. The output range could have been set as 0.1V to 4.9V to match the linear range, but in this example design margin is added to account for power supply variation.
2. Use the Analog Engineer's Calculator in the next step to select component values. Enter the input and output voltages and reference voltage (–10V < V_IN < +10V, and 0.2V < V_OUT < 4.8V). The range of acceptable reference voltages is given at the bottom of the tool (3.35V to 12V, in this example). A reference of 5V is selected as this reference voltage is available elsewhere in the circuit. The tool outputs the 0.1% resistors required to map the voltages (R_a = 10kΩ, R_b = 8.56kΩ, R_c = 4.59kΩ).
   
3. The following equations show the transfer function for the non-inverting level-shift topology. It is possible to use these equations to solve for the different component values rather than the calculator. To do this, choose a reference value and fix the value of R_a to 10kΩ. Once this is done, solve for R_b and R_c for two different values of output signal. The algebra for this problem is a little complex, so the calculator is the suggested method. Use the equations to verify the transfer function as the equation following shows.
   

   where

   • 

     Using the values from the calculator:

     R_a = 10kΩ, R_b = 8.56kΩ, R_c = 4.59kΩ
     V_O = 0.23005V × V_IN + 2.506V
     V_O(–10V) = 0.2055V
     V_O(+10V) = 4.8065V
4. Find Rfilt and Cfilt to allow for settling at 1Msps. The Refine the Rfilt and Cfilt Values on ADC drive video from the TI Precision Labs - ADCs video series shows the algorithm for selecting Rfilt and Cfilt. The final value of 24.9Ω and 1.1nF proved to settle to well below ½ of a least significant bit (LSB).

DC Transfer Characteristics

The following graph shows the linear output response for a –10V to 10V input. In this case, the amplifier output is approximately 0.2V for a –10V input and 4.8V for a +10V input. This design was scaled so that the output range avoids the nonlinear power supply rails by 0.2V. See the TI Precision Labs - ADCs Determining a SAR ADC's Linear Range when using operational amplifiers video for detailed theory on this subject.

AC Transfer Characteristics

The bandwidth is limited by the RC charge bucket circuit. The calculated and simulated bandwidth compare well (calculated f_c = 2.9MHz, simulated f_c = 4.06MHz). The small discrepancy in the bandwidth is due to gain peaking on the OPA320 device.

Transient ADC Input Settling Simulation

The following simulation shows settling to a +10-V DC input signal. This type of simulation shows that the sample and hold kickback circuit is properly selected. See the Final SAR ADC Drive Simulations video for detailed theory on this subject.

Noise Simulation

The following noise calculation takes into account the thermal noise of the resistor network, the amplifier noise, and the bandwidth limit from the RC filter. The calculated total noise is 23.5µV_RMS and the simulated total noise is 21.04µV_RMS. See the Op Amp Noise Calculation video for detailed theory on amplifier noise calculations, and the Calculating the total noise for ADC Systems video for data converter noise.

Noise equivalent input resistor network:

Resistor network noise:

OPS320 noise density:

Total noise:

Design Featured Devices and Alternative Parts

Link to Key Files

Texas Instruments, SBAC250 sources files, software support