SBAA493A June 2021 – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

3 Target Mode Power Consumption with PLL Disabled

Table 3-1 describes the typical current consumption of the TLV320ADCx120/PCMx120-Q1 when the PLL is disabled with AVDD set to 1.8 V and 3.3 V. The PLL is disabled by:

Clearing the bit field PLL_PDZ in the PWR_CFG register
Applying a controller clock through BCLK, GPIO1, or the GPIx pins
- If GPIO1 is configured as MCLK, setting the appropriate GPIO1_CFG bit field in the GPIO_CFG0 register
- If GPIx is configured as MCLK, setting the appropriate GPIx_CFG bit field in the GPI_CFG0 register
Indicating the controller clock source through DIS_PLL_SLV_CLK_SRC bit field in the CLK_SRC register
Setting the appropriate MCLK to FSYNC ratio through the MCLK_RATIO_SEL bit field and MCLK_FREQ_SEL_MODE bit field of the CLK_SRC register
Setting the AUTO_MODE_PLL_DIS bit field and the corresponding MCLK_FREQ_SEL bit field of the MST_CFG0 register

In this table, when the DRE was enabled, the DRE threshold was set to –36 dB. The power consumption measurements had the Biquad Filters disabled and inputs grounded.

Table 3-1 Typical Current Consumption (PLL Disabled)

SAMPLING FREQUENCY (kHz)	MCLK FREQUENCY (MHz)	MCLK RATIO	ADC CHANNELS	DRE	DECIMATION FILTERS	BCLK RATIO	WORD LENGTH	AVDD CURRENT AT 3.3 V (mA)	AVDD CURRENT AT 1.8 V (mA)
8	12.288	1536	1	Disabled	Linear Phase	32	32	5.68	5.41
8	12.288	1536	2	Disabled	Linear Phase	48	24	9.91	9.33
16	12.288	768	1	Disabled	Linear Phase	24	24	5.67	5.59
				Enabled	Linear Phase			6.13	5.87
				Disabled	Low Latency			5.74	5.66
				Enabled	Low Latency			6.20	5.94
				Disabled	Ultra-Low Latency			5.63	5.55
				Enabled	Ultra-Low Latency			5.90	5.83
			2	Disabled	Linear Phase	48		10.24	9.65
				Disabled	Low Latency			10.38	9.79
				Disabled	Ultra-Low Latency			10.15	9.57
16	24.576	1536	1	Disabled	Linear Phase	24	24	6.16	5.83
				Enabled	Linear Phase			6.24	6.11
				Disabled	Low Latency			6.23	5.85
				Enabled	Low Latency			6.50	6.19
				Disabled	Ultra-Low Latency			6.16	5.79
				Enabled	Ultra-Low Latency			6.39	6.07
			2	Disabled	Linear Phase	48		10.58	9.91
				Enabled	Linear Phase			11.13	10.46
				Disabled	Low Latency			10.72	9.97
				Enabled	Low Latency			10.91	10.60
				Disabled	Ultra-Low Latency			10.50	9.82
				Enabled	Ultra-Low Latency			11.05	10.37
				Disabled	Linear Phase	96		10.59	9.91
				Enabled	Linear Phase			11.11	10.47
				Disabled	Low Latency			10.73	10.06
				Enabled	Low Latency			11.28	10.61
				Disabled	Ultra-Low Latency			10.14	9.83
				Enabled	Ultra-Low Latency			10.70	10.38
16	36.864	2304	1	Disabled	Linear Phase	24	24	6.46	6.21
				Enabled	Linear Phase			6.74	6.48
				Disabled	Low Latency			6.53	6.17
				Enabled	Low Latency			6.81	6.46
				Disabled	Ultra-Low Latency			6.42	6.05
				Enabled	Ultra-Low Latency			6.70	6.35
			2	Disabled	Linear Phase	48		10.89	10.09
				Enabled	Linear Phase			11.44	10.63
				Disabled	Low Latency			11.03	10.23
				Enabled	Low Latency			11.58	10.79
				Disabled	Ultra-Low Latency			10.80	10.01
				Enabled	Ultra-Low Latency			11.35	10.59
				Disabled	Linear Phase	96		10.90	10.09
				Enabled	Linear Phase			11.45	10.63
				Disabled	Low Latency			11.04	10.25
				Enabled	Low Latency			11.59	10.79
				Disabled	Ultra-Low Latency			10.81	10.02
				Enabled	Ultra-Low Latency			11.36	10.56
24	12.288	512	1	Disabled	Linear Phase	24	24	5.97	5.58
				Enabled	Linear Phase			6.31	5.93
				Disabled	Low Latency			6.11	5.73
				Enabled	Low Latency			6.28	6.07
				Disabled	Ultra-Low Latency			5.93	5.54
				Enabled	Ultra-Low Latency			6.27	5.88
			2	Disabled	Linear Phase	48		10.05	9.69
					Ultra-Low Latency	64	32	10.35	9.56
					Linear Phase	96	24	10.45	9.70
					Ultra-Low Latency	96	24	10.32	9.62
	24.576	1024	1	Disabled	Linear Phase	32	32	6.29	5.95
				Enabled	Linear Phase			6.36	6.29
				Disabled	Low Latency			6.44	6.09
				Enabled	Low Latency			6.52	6.43
				Disabled	Ultra-Low Latency			6.25	5.91
				Enabled	Ultra-Low Latency			6.34	6.25
			2	Disabled	Linear Phase	64		10.77	10.11
				Enabled	Linear Phase			10.90	10.78
				Disabled	Low Latency			11.06	10.40
				Enabled	Low Latency			12.46	10.81
				Disabled	Ultra-Low Latency			10.32	10.02
				Enabled	Ultra-Low Latency			10.84	10.49
				Disabled	Linear Phase	128		10.79	10.12
				Enabled	Linear Phase			10.91	10.79
				Disabled	Low Latency			11.07	10.41
				Enabled	Low Latency			12.32	11.08
				Disabled	Ultra-Low Latency			10.70	10.04
				Enabled	Ultra-Low Latency			10.86	10.70
24	36.864	1536	1	Disabled	Linear Phase	24	24	6.58	6.20
				Enabled	Linear Phase			6.91	6.53
				Disabled	Low Latency			6.72	6.35
				Enabled	Low Latency			7.06	6.68
				Disabled	Ultra-Low Latency			6.53	6.17
				Enabled	Ultra-Low Latency			6.87	6.50
			2	Disabled	Linear Phase	48		11.09	10.26
				Enabled	Linear Phase			11.72	10.94
				Disabled	Low Latency			11.37	10.58
				Enabled	Low Latency			12.03	11.22
				Disabled	Ultra-Low Latency			11.00	10.22
				Enabled	Ultra-Low Latency			11.45	10.89
				Disabled	Linear Phase	96		11.10	10.27
				Enabled	Linear Phase			11.76	10.96
				Disabled	Low Latency			11.38	10.59
				Enabled	Low Latency			11.73	11.25
				Disabled	Ultra-Low Latency			11.01	10.23
				Enabled	Ultra-Low Latency			11.67	10.92
32	12.288	384	1	Disabled	Linear Phase	24	24	6.05	5.65
				Enabled	Linear Phase			6.45	6.05
				Disabled	Low Latency			6.05	5.65
				Enabled	Low Latency			6.45	5.99
				Disabled	Ultra-Low Latency			5.93	5.53
				Enabled	Ultra-Low Latency			6.33	5.93
				Disabled	Linear Phase	48		10.56	9.84
					Ultra-Low Latency	48		9.79	9.36
					Linear Phase	96		10.57	9.85
					Ultra-Low Latency	96		10.33	9.61
	24.576	768	1	Disabled	Linear Phase	24	24	6.40	5.96
				Enabled	Linear Phase			6.81	6.37
				Disabled	Low Latency			6.40	5.97
				Enabled	Low Latency			6.81	6.38
				Disabled	Ultra-Low Latency			6.29	5.86
				Enabled	Ultra-Low Latency			6.69	6.27
			2	Disabled	Linear Phase	48		10.97	10.02
				Enabled	Linear Phase			11.76	10.80
				Disabled	Low Latency			10.73	10.04
				Enabled	Low Latency			11.59	10.82
				Disabled	Ultra-Low Latency			10.73	9.82
				Enabled	Ultra-Low Latency			11.52	10.60
				Disabled	Linear Phase	96		10.98	10.03
				Enabled	Linear Phase			11.77	10.82
				Disabled	Low Latency			10.98	10.06
				Enabled	Low Latency			11.76	10.84
				Disabled	Ultra-Low Latency			10.74	9.82
				Enabled	Ultra-Low Latency			10.27	10.61
48	12.288	256	1	Disabled	Linear Phase	24	24	6.37	5.99
					Low Latency			6.27	5.89
					Ultra-Low Latency			6.10	5.72
	24.576	512		Disabled	Linear Phase	32	32	6.70	6.35
				Enabled	Linear Phase			7.22	6.87
				Disabled	Low Latency			6.60	6.26
				Enabled	Low Latency			7.13	6.78
				Disabled	Ultra-Low Latency			6.43	6.09
				Enabled	Ultra-Low Latency			6.95	6.61
			2	Disabled	Linear Phase	64		11.48	10.82
					Low Latency			11.30	10.63
					Ultra-Low Latency			10.95	10.28
					Linear Phase	128		11.51	10.85
					Low Latency			11.33	10.66
					Ultra-Low Latency			10.98	10.31
48	36.864	768	1	Disabled	Linear Phase	24	24	6.78	6.72
				Enabled	Linear Phase			7.28	7.24
				Disabled	Low Latency			6.71	6.63
				Enabled	Low Latency			7.26	7.14
				Disabled	Ultra-Low Latency			6.55	6.45
				Enabled	Ultra-Low Latency			7.09	6.97
			2	Disabled	Linear Phase	48		11.34	11.21
				Enabled	Linear Phase			12.37	12.22
				Disabled	Low Latency			11.20	11.02
				Enabled	Low Latency			12.21	12.03
				Disabled	Ultra-Low Latency			10.87	10.68
				Enabled	Ultra-Low Latency			11.88	11.68
				Disabled	Linear Phase	96		11.36	11.23
				Enabled	Linear Phase			12.37	12.24
				Disabled	Low Latency			11.22	11.04
				Enabled	Low Latency			12.23	12.05
				Disabled	Ultra-Low Latency			10.89	10.70
				Enabled	Ultra-Low Latency			11.88	11.70
96	24.576	256	1	Disabled	Linear Phase	32	32	7.80	7.45
					Low Latency			7.60	7.25
					Ultra-Low Latency			7.25	6.90
	36.864	384			Linear Phase	24	24	7.83	7.80
				Enabled	Linear Phase			8.85	8.83
				Disabled	Low Latency			7.68	7.60
				Enabled	Low Latency			8.70	8.63
				Disabled	Ultra-Low Latency			7.34	7.26
				Enabled	Ultra-Low Latency			8.37	8.28
			2	Disabled	Linear Phase	48		13.25	13.17
					Low Latency			12.94	12.76
					Ultra-Low Latency			12.25	12.08