SBAA493A June   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Target Mode Power Consumption With PLL Enabled
  4. 3Target Mode Power Consumption with PLL Disabled
  5. 4Digital Microphone Power Consumption
  6. 5Settings for Lowest Power Consumption
  7. 6Related Documentation
  8. 7Revision History

1 Introduction

Power consumption on TLV320ADCx120/PCMx120-Q1 devices is highly dependent on the usage scenario and features enabled on these devices. The following tables summarize the power consumption based on the following:

  • Supply voltage
  • Sampling Frequency (FS)
  • Number of channels
  • DRE enabled or disabled
  • Decimation filter options
  • Bit clock (BCLK) to Frame sync (FSYNC) ratio
  • PLL enabled or disabled
  • Converted word length

The tables report the average active current consumed on the Analog Supply, AVDD. This supply includes all the internal analog and digital circuits, but excludes the current consumed by the I/O pins due to its application dependencies. I/O power is dependent upon the following:

  • Load capacitance of the system bus interface
  • Data output clock rate
  • Data conversion output activity
  • Bus interface pullups or pulldowns
  • Frequency of ADC commands sent by microprocessor