SBAA494A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Processing Blocks of TLV320ADCx120 and PCMx120-Q1
    1. 2.1 Decimation Filter Response
      1. 2.1.1 Supported Sample Rates
    2. 2.2 AGC, DRE, or DRC
      1. 2.2.1 Supported Sample Rates
      2. 2.2.2 Channel Assignment
    3. 2.3 Channel Summer, Digital Mixer, and Bi-quads
  4. 3Processing Blocks Supported for Different Sample Rates
    1. 3.1 8 kHz Sample Rate
    2. 3.2 16 kHz-48 kHz Sample Rate
    3. 3.3 96 kHz Sample Rate
    4. 3.4 192 kHz Sample Rate
    5. 3.5 384 kHz Sample Rate
    6. 3.6 768 kHz Sample Rate
  5. 4Example Configurations
  6. 5Related Documentation
  7.   A Revision History

2.2 AGC, DRE, or DRC

Analog channels include a processing block that supports one of the following options:

  • Automatic Gain Control (AGC) is an algorithm that dynamically controls the gain of the ADC channel to maintain a nominally constant output level. AGC is available on all TLV320ADCx120 and PCMx120-Q1 device variants.
  • Dynamic Range Enhancer (DRE) is an algorithm that dynamically adjusts the PGA gain of the ADC channel to enhances the dynamic range. DRE is available on the TLV320ADC5120, TLV320AD6120, PCM5120-Q1, and PCM6120-Q1 devices.
  • Dynamic Range Compression (DRC) is an algorithm that dynamically adjusts the PGA gain of the ADC channel to expand the signal level over an region of the audio range. DRC is available on the TLV320ADC5120, TLV320AD6120, PCM5120-Q1, and PCM6120-Q1 devices.

Only one of these blocks can be enabled at a time. These blocks are enabled by setting the appropriate DRE_AGC_SEL and DRC_EN bit fields in DSP_CFG1 (P0_R108) as shown in Table 2-3.

Table 2-3 AGC, DRE, or DRC Selection Register Field Description
Processing BlockP0_R108_D[3] : AGC_SEL[0]P0_R108_D[1] : DRC_EN[0]
AGC10
DRE0 (default)0 (default)
DRC01

The TLV320ADC5120, TLV320AD6120, PCM5120-Q1, and PCM6120-Q1 devices also support enhanced version of the AGC, DRE, or DRC algorithms by setting the ENH_DRE_AGC_DRC bit field in the DSP_CFG0 (Po_R107[6])