SBAA495A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 I2S and LJF Standard Bus Formats
    2. 3.2 Support for Non-Standard I2S and LJF Bus Formats
  6. 4Related Documentation
  7.   A Revision History

3.1 I2S and LJF Standard Bus Formats

In standard I2S and LJF bus formats, the FSYNC edge is synchronous to the falling edge of BCLK. Figure 3-1 and Figure 3-2 show the timing diagrams supported by TLV320ADCx120 and PCMx120-Q1 in I2S and LJF mode, respectively.

GUID-27FAEB63-E2CE-4467-892A-18A93E46761F-low.gifFigure 3-1 Default I2S Format in Controller Mode (TX_OFFSET = 0)
GUID-4905BE3F-BC1D-48F0-8A17-358D21785C27-low.gifFigure 3-2 Default LJF Format in Controller Mode (TX_OFFSET = 0)