SBAA495A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 I2S and LJF Standard Bus Formats
    2. 3.2 Support for Non-Standard I2S and LJF Bus Formats
  6. 4Related Documentation
  7.   A Revision History

2.1.2.2 Example

For a 24.576-MHz or 22.579-MHz MCLK, the following I2C script configures the TLV320ADCx120 and PCMx120-Q1 as controller mode with GPIO1 as MCLK input for the 48-kHz or 44.1-kHz sampling rate, respectively:

w 9C 13 a0 # enable controller mode, disable PLL for auto-clock config w 9C 14 48 # FS = 44.1/48k BCLK/fsync ratio = 256 w 9C 16 d8 # MCLK is audio root, use MCLK_ratio_sel, MCLK/Fsync ratio = 512 w 9C 21 a0 # configure GPIO1 as MCLK input