SBAA495A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 I2S and LJF Standard Bus Formats
    2. 3.2 Support for Non-Standard I2S and LJF Bus Formats
  6. 4Related Documentation
  7.   A Revision History

2.1.2 Auto Clock Detect With PLL Disabled

For the lowest power consumption, it can be desirable to disable the PLL and derive all clocks directly from MCLK. To disable the PLL in auto configuration mode, set bit 5 (AUTO_MODE_PLL_DIS) in MST_CFG0 (page 0, register 0x13). The required inputs for this mode are found in Table 2-5.

Table 2-5 Required Input Parameters for Controller Mode Auto Clock Configuration With PLL Disabled
USER-PROVIDED PARAMETERREGISTER
FS MODEPage 0, MST_CFG0 Register 0x13, Bit 3
FS_RATEPage 0, MST_CFG1 Register 0x14, Bits 7-4
FS_BCLK_RATIOPage 0, MST_CFG1 Register 0x14, Bits 3-0
MCLK_FREQ_SEL_MODEPage 0, CLK_SRC Register 0x16, Bit 6
MCLK_RATIO_SELPage 0, CLK_SRC Register 0x16, Bits 5-3