SBAA528 February   2022 ADC12QJ1600-Q1 , TPS62912 , TPS62913

 

  1.   Trademarks
  2. 1Introduction and System Description
    1. 1.1 Introduction
      1. 1.1.1 ADC12QJ1600-Q1 Noise and Ripple Requirements
      2. 1.1.2 Power Supply Requirements for Clocks
      3. 1.1.3 TPS62913 Low-Noise and Low-Ripple Buck Converter
    2. 1.2 Block Diagram
    3. 1.3 Design Considerations
  3. 2Tests and Results
    1. 2.1 Test Methodology
    2. 2.2 Test Conditions
    3. 2.3 Test Results
  4. 3Conclusion
  5. 4References
  6.   A Appendix

3 Conclusion

As shown by the test results, a simplified power supply design using the TPS62913 low-ripple and low-noise buck converts can provide similar performance to the traditional SMPS + LDO approach. The Analog, Digital, and Clock rails are all supplied using the switching regulator without the need for a low-dropout linear regulator (LDO) while maintaining the same performance as the original design. The SNR, SFDR, and NSD performance with spread spectrum and without spread spectrum is similar to the SMPS + LDO approach. Use of the TPS62913 design reduces the power consumption by 1.908W (32% power savings), reduces the size of the design, and reduces the temperature rise of the power supply components.

Although this design used the ADC12QJ1600-Q1, other ADCs that require low noise power supplies that are size constrained and thermal constrained can also use this approach.