3 What Causes Conversion Latency in a Delta-Sigma ADC?

A basic introduction to how a delta-sigma ADC works is helpful to understand why this data converter architecture inherently results in conversion latency. When a conversion start is triggered, the delta-sigma modulator continuously oversamples the analog input using a high-frequency clock, f_MOD. The modulator outputs a digital bitstream at f_MOD that has a ones density proportional to the input signal: the modulator outputs all zeros when the input is at negative full-scale (–FS), all ones when the input is at positive full-scale (+FS), and a proportional number of ones and zeros between these two extremes. Figure 3-1 shows how the analog input signal in black is applied to the delta-sigma modulator, which generates the digital bitstream in green using the high-frequency modulator clock in red.

Figure 3-1 Delta-Sigma Modulator Bitstream Output for an Arbitrary Analog Input

As each bit of the green modulator bitstream in Figure 3-1 is generated, it propagates through the digital filter to be averaged and decimated. After a well-defined number of clock cycles, a high-resolution output is produced. Figure 3-2 generalizes delta-sigma ADC digital filter behavior using a simplified model.

Figure 3-2 Simplified Digital Filter Model

The model in Figure 3-2 has N number of stages that are each comprised of one delay block (DB_X) in purple and one multiplier in orange, while the summing junction in blue aggregates the information in all stages to produce the filtered, decimated output. As each bit of the green bitstream enters the filter, it progresses through the delay blocks one modulator clock period (t_MOD = 1 / f_MOD) at a time. The digital filter only produces the filtered, decimated output in blue when the first bit in the sequence reaches the last delay block. Assuming that the ADC is sampling continuously, this sequence restarts during the subsequent t_MOD period and generates the next output after N number of t_MOD periods have elapsed. Therefore, a digital filter with N number of delay blocks and a decimation ratio of N has a conversion period, t_CP, given by Equation 1:

The variable N in Equation 1 and Figure 3-2 is often referred to as the oversampling ratio (OSR). The OSR determines how many samples are averaged together during one conversion period. As Equation 1 implies, the larger the value of N (OSR), the longer it takes to generate the output. However, a larger value of N (OSR) generally leads to lower noise because of additional averaging.

As an example of this behavior, Figure 3-3 shows how the red modulator clock and green bitstream from Figure 3-1 are applied to the digital filter model in Figure 3-2. In this example, the digital filter has four delay blocks (N = 4) and the first four bits of the bitstream have an arbitrary value of 1011b.

Figure 3-3 Modulator Bitstream Propagating Through a Digital Filter When N = 4

As shown during the fourth modulator period in Figure 3-3, t_CP = 4 ∙ t_MOD, which is the time it takes for the bitstream to reach the last delay block in this example. Therefore, the number of digital filter delay blocks is the dominant factor causing delta-sigma ADC conversion latency. The next section expands on this topic by using the digital filter model in Figure 3-2 to analyze the different types of low-latency filters commonly used in delta-sigma ADCs and how they respond to an analog input signal.

Further discussion of delta-sigma ADC modulator operation and digital filter design are beyond the scope of this article. See the Digital Filter Types in Delta-Sigma ADCs application note and TI’s Precision Labs ADC content for more information.