SBAA535A March   2022  – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Data Sheet Timing and Nomenclature
  6. 3 What Causes Conversion Latency in a Delta-Sigma ADC?
  7. 4 Digital Filter Operation and Behavior
    1.     8
    2.     9
    3. 4.1 Unsettled Data Due to an ADC Operation
  8. 5 ADC Features and Modes that Affect Conversion Latency
    1. 5.1 First Conversion Versus Second and Subsequent Conversion Latency
    2. 5.2 Conversion Mode
    3. 5.3 Programmable Delay
    4. 5.4 ADC Overhead Time
    5. 5.5 Clock Frequency
    6. 5.6 Chopping
  9. 6 Analog Settling
  10. 7 Important Takeaways
  11. 8 Cycle Time Calculation Examples
    1. 8.1 Example #1: Using the ADS124S08
    2. 8.2 Example #2: Changing the Conversion Mode
    3. 8.3 Example #3: Changing the Filter Type
    4. 8.4 Example #4: Changing the Clock Frequency
    5. 8.5 Example #5: Enabling Chop and Reducing the Number of Conversions per Channel
    6. 8.6 Example #6: Scanning Two Channels With Different System Parameters
    7. 8.7 Example #7: Using the ADS1261
    8. 8.8 Example #8: Changing Multiple Parameters Using the ADS1261
  12. 9 Summary
  13. 10Revision History

2 Data Sheet Timing and Nomenclature

The first step toward understanding delta-sigma ADC timing and operation is to define a common vocabulary that describes this behavior. Table 2-1 identifies five key parameters that serve as the foundation for the rest of this document.

Table 2-1 Important Delta-Sigma ADC Timing and Operation Parameters .
PARAMETER DEFINITION
Conversion period The time during which the delta-sigma modulator samples the analog input, filters the data, and decimates the output
Conversion latency The time the ADC takes to produce settled output data:
  • Assumes a settled analog input
  • Can span a single conversion period or multiple conversion periods
  • Can include processing time such as ADC overhead or programmable delay
Conversion result Data retrieved by the user after the ADC indicates new results are ready:
  • Can be a combination of multiple conversions
  • Can be settled or unsettled
Channel scan time The time to generate the desired number of conversion results for a given channel – can be equal to conversion latency if the system only requires one conversion result per channel
System cycle time The total time required to perform one complete loop through all measurement channels – can be equal to channel scan time if the system only measures one channel

A delta-sigma ADC data sheet uses the information in Table 2-1 to describe ADC timing behavior in several different ways. One such way that an ADC data sheet communicates timing behavior is using a conversion latency table. This information is important for those devices that have multiple filter types and output data rates (ODRs). For example, Table 2-2 shows the conversion latency in milliseconds for the 24-bit, 40-kSPS, 10-channel ADS1261.

Table 2-2 ADS1261 Conversion Latency (ms)1
ODR (SPS)FIRSINC1SINC2SINC3SINC4SINC5
2.5402.2400.4800.412001600—
5202.2200.4400.4600.4800.4—
10102.2100.4200.4300.4400.4—
16.6—60.43120.4180.4240.4—
2052.2350.43100.4150.4200.4—
50—20.4340.4360.4380.43—
60—17.0933.7650.4367.09—
100—10.4320.4330.4340.43—
400—2.9255.4257.92510.43—
1200—1.2582.0912.9253.758—
2400—0.8411.2581.6752.091—
4800—0.6330.8411.051.258—
7200—0.5640.7020.8410.98—
14400—————0.423
19200—————0.336
25600—————0.271
40000—————0.179
(1) Chop mode off, conversion-start delay = 50µs (DELAY[3:0] = 0001)

Table 2-2 provides a conversion latency value for each combination of ODR and filter type using the ADS1261. In this particular case, the ADS1261 conversion latency time is specified using the nominal clock frequency as well as chop mode turned off and a programmable delay of 50µs, as per the table note for Table 2-2. Other ADCs might specify the conversion latency time using different parameters, different conditions, or even a different format, but the same general information is always provided. This application note delves into the details of these tables to identify the factors contributing to conversion latency and how this relates to overall cycle time.

Additionally, ADC data sheets often use timing diagrams to help visualize the general timing behavior. Figure 2-1 shows an example timing diagram for a typical multiplexed delta-sigma ADC. This timing diagram shows how different conversion results can be comprised of a different number of conversion periods (tCP) and conversion latencies (tCL), as well as include fixed timing parameters (delay and overhead). The channel scan time (tCH) and system cycle time (tCYCLE) are also shown. In this example, tCH = tCYCLE because only one channel is measured.

GUID-20220201-SS0I-TJGW-7XMM-LLNZDCWLJZFW-low.svgFigure 2-1 Generic Delta-Sigma ADC Timing Diagram

Many of the timing parameters defined in Table 2-1 are also shown in Figure 2-1. Furthermore, this application note uses diagrams similar to Figure 2-1 to help visualize how each ADC timing component affects the conversion period, conversion latency, channel scan time, or system cycle time.

Finally, additional ADC features or even some external factors can impact the device timing behavior. These features are often described in separate data sheet sections, making it challenging to determine how each contributes to the overall latency for a specific device. This application note organizes this information into one document to provide a more complete view of ADC operation and how this affects timing.

The rest of this document explores these three components of a delta-sigma ADC data sheet in detail to provide a comprehensive understanding of how multiplexed delta-sigma ADCs sample and process data, and how this contributes to conversion latency and overall system cycle time.