SBAA611 October   2024 TAC5111 , TAC5112 , TAC5211 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TAC5212 and TAC5211 Power Consumption
    1. 2.1 TAC521x: Target Mode Power Consumption With PLL Disabled
    2. 2.2 TAC521x: Target Mode Power Consumption with PLL Enabled
  6. 3TAC5112 and TAC5111 Power Consumption
    1. 3.1 TAC511x: Target Mode Power Consumption With PLL Disabled
    2. 3.2 TAC511x: Target Mode Power Consumption With PLL Enabled
  7. 4Settings for Lowest Power Consumption
    1. 4.1 Power Tune Options
  8. 5Summary
  9. 6References

4.1 Power Tune Options

TAC5x1x also features a group of power tune settings aimed toward reducing further current consumption by optimizing the power consumed in the analog signal chain and the MIPS required by the DSP. These power tune options can be found in PWR_TUNE_CFG0 and PWR_TUNE_CFG1 for ADC and DAC, respectively. The power tune options exercised include the following:

  • ADC Power Tune options
    • Modulator Clock by 2 Mode: This mode reduces the modulator clock of the ADC to 1.5MHz from the default 3MHz.
      • For AVDD > 2V, this mode is only applicable in ADC 10k input impedance (ADC_CHx_IMP) along with rail-to-rail common mode configuration (ADC_CHx_CM_TOL).
    • CIC Filter Order: This mode reduces the number of CIC filter stages from 5th order to 4th order.
    • Low Power Filter: This mode when set, overrides the ADC decimation filters to reduce the MIPS required by the DSP to the lowest possible. This mode is used in conjunction with the PLL disabled condition to efficiently utilize the reduced MIPS available for the DSP.
  • DAC Power Tune options
    • Modulator Clock by 2 Mode: This mode when set, reduces the modulator clock of the DAC to 1.5MHz from the default 3MHz.
    • DAC Power Scale: This mode when set, reduces intermediate current stages in the DAC by half (VREF/2R).
    • Low Power Filter: This mode when set, overrides the DAC decimation filters to reduce the MIPS required by the DSP to the lowest possible. This mode is used in conjunction with the PLL disabled condition, to efficiently utilize the reduced MIPS available for the DSP.

To access the power tune current consumption matrix, select this Excel link.