To minimize the power consumption of the TAC5x1x devices, verify that unused modules are disabled, use the lowest sampling rate, bit clock, and controller clock required by the application, and operate at the lowest AVDD and IOVDD supply voltages possible. The following list summarizes the settings and registers for lowest power operation:
- Operate at the lowest supply voltage possible. AVDD and IOVDD support a 1.8V or 3.3V supply, independently (AVDD and IOVDD can have different supply voltages).
- Unused analog inputs, tie to analog ground.
- Unused digital inputs, tie to digital ground.
- Unused outputs, leave unconnected.
- Disable unused DAC and ADC and PDM channels through the CH_EN register.
- Disable MICBIAS power, if unused, through the PWR_CFG register.
- Operate at the lowest sample rate possible.
- Disable PLL if the system supplies a low jitter controller clock (these
settings are discussed in the PLL Disabled
sections, refer to the Table of Contents).
- Disable unused post-processing blocks:
- Disable biquad filters, if unused, through the DSF_CFG0 and DST_CFG1 registers for ADC and DAC, respectively.
- Select ultra-low latency filters over linear-phase decimation filters, if the application allows, through the DSP_CFGx register.
- Use the smallest word length allowed by the application for the primary and secondary audio serial interfaces (ASI), using PASI_CFG0 and SASI_CFG0, respectively.