SBAA611 October   2024 TAC5111 , TAC5112 , TAC5211 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TAC5212 and TAC5211 Power Consumption
    1. 2.1 TAC521x: Target Mode Power Consumption With PLL Disabled
    2. 2.2 TAC521x: Target Mode Power Consumption with PLL Enabled
  6. 3TAC5112 and TAC5111 Power Consumption
    1. 3.1 TAC511x: Target Mode Power Consumption With PLL Disabled
    2. 3.2 TAC511x: Target Mode Power Consumption With PLL Enabled
  7. 4Settings for Lowest Power Consumption
    1. 4.1 Power Tune Options
  8. 5Summary
  9. 6References

1 Introduction

Power consumption in TAC5x1x devices is highly dependent on the enabled usage and features. The following tables summarize power consumption across:

  • Supply voltage
  • Sampling frequency
  • Enabled channel count
  • Decimation filter
  • Bit clock to frame sync ratio
  • PLL state (enabled or disabled)
  • Output configuration and loads
  • Converted word length

The following tables report the average idle-channel current consumed on the AVDD analog supply. This supply powers all the internal analog and digital circuits. Depending on the application, the input/output (I/O) supply, IOVDD, is excluded as the current is consumed by the digital I/O pins. I/O power is dependent upon:

  • The load capacitance of the system bus interface
  • The digital data I/O clock rate
  • The I2C bus interface pull-up and frequency of transactions performed by the host