SBAK019A July   2024  – November 2024 ADC3683-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-Up (SEL) Results
  11. 8 Single-Event Transients (SET)
    1. 8.1 Single Event Transients
  12. 9 Event Rate Calculations
  13. 10Summary
  14. 11References
  15. 12Revision History

5 Depth, Range, and LETEFF Calculation

The ADC3683-SP is fabricated in the TI CMOS C021(C021, 65nm process with a Back-End-Of-Line (BEOL) stack consisting of eight levels of standard thickness aluminum metal. The total stack height from the surface of the passivation to the silicon surface is 20.7μm based on nominal layer thickness. Accounting for energy loss through the 1mil thick Aramica beam port window, the 40mm air gap and the BEOL stack over the ADC3683-SP, the effective LET (LETEFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the SEUSS 2020 software that was provided by the Texas A&M University Cyclotron Institute and based on the latest SRIM-2013models (4, 5). Table 5-1 lists the results.

Table 5-1 Ion LETEFF Depth and Range in Silicon
Ion TypeAngle of Incidence (°)RangeEFF in Silicon (µm)LETEFF (MeV × cm2/mg)

165Ho

0

78.4

78.36

141Pr3068.178.67
141Pr081.967.45
109Ag3063.559.82
109Ag076.651.12
63Cu010221.44