SBAS426H August   2008  – March 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Timing Requirements
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  ADC Input and Multiplexer
      2. 9.3.2  Low-Noise PGA
        1. 9.3.2.1 PGA Common-Mode Voltage Requirements
        2. 9.3.2.2 PGA Common-Mode Voltage Calculation Example
        3. 9.3.2.3 Analog Input Impedance
      3. 9.3.3  Clock Source
      4. 9.3.4  Modulator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Voltage Reference Input
      7. 9.3.7  Internal Voltage Reference
      8. 9.3.8  Excitation Current Sources
      9. 9.3.9  Sensor Detection
      10. 9.3.10 Bias Voltage Generation
      11. 9.3.11 General-Purpose Digital I/O
      12. 9.3.12 System Monitor
        1. 9.3.12.1 Power-Supply Monitor
        2. 9.3.12.2 External Voltage Reference Monitor
        3. 9.3.12.3 Ambient Temperature Monitor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Up
      2. 9.4.2 Reset
      3. 9.4.3 Power-Down Mode
      4. 9.4.4 Conversion Control
        1. 9.4.4.1 Settling Time for Channel Multiplexing
        2. 9.4.4.2 Channel Cycling and Overload Recovery
        3. 9.4.4.3 Single-Cycle Settling
        4. 9.4.4.4 Digital Filter Reset Operation
      5. 9.4.5 Calibration
        1. 9.4.5.1 Offset Calibration Register: OFC[2:0]
        2. 9.4.5.2 Full-Scale Calibration Register: FSC[2:0]
        3. 9.4.5.3 Calibration Commands
          1. 9.4.5.3.1 System Offset and Self Offset Calibration
          2. 9.4.5.3.2 System Gain Calibration
        4. 9.4.5.4 Calibration Timing
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Ready (DRDY)
        5. 9.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 9.5.1.6 SPI Reset
        7. 9.5.1.7 SPI Communication During Power-Down Mode
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  WAKEUP (0000 000x)
        2. 9.5.3.2  SLEEP (0000 001x)
        3. 9.5.3.3  SYNC (0000 010x)
        4. 9.5.3.4  RESET (0000 011X)
        5. 9.5.3.5  RDATA (0001 001x)
        6. 9.5.3.6  RDATAC (0001 010x)
        7. 9.5.3.7  SDATAC (0001 011x)
        8. 9.5.3.8  RREG (0010 rrrr, 0000 nnnn)
        9. 9.5.3.9  WREG (0100 rrrr, 0000 nnnn)
        10. 9.5.3.10 SYSOCAL (0110 0000)
        11. 9.5.3.11 SYSGCAL (0110 0001)
        12. 9.5.3.12 SELFOCAL (0110 0010)
        13. 9.5.3.13 NOP (1111 1111)
        14. 9.5.3.14 Restricted Command (1111 0001)
    6. 9.6 Register Maps
      1. 9.6.1 ADS1246 Register Map
      2. 9.6.2 ADS1246 Detailed Register Definitions
        1. 9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h]
        2. 9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h]
        4. 9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = PGA dependent]
        7. 9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h]
      3. 9.6.3 ADS1247 and ADS1248 Register Map
      4. 9.6.4 ADS1247 and ADS1248 Detailed Register Definitions
        1. 9.6.4.1  MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h]
        2. 9.6.4.2  VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.4.3  MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h]
        4. 9.6.4.4  SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.4.5  OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.4.6  FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = PGA dependent]
        7. 9.6.4.7  IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h]
        8. 9.6.4.8  IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh]
        9. 9.6.4.9  GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h]
        10. 9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h]
        11. 9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
      8. 10.1.8 Channel Multiplexing Example
      9. 10.1.9 Power-Down Mode Example
    2. 10.2 Typical Applications
      1. 10.2.1 Ratiometric 3-Wire RTD Measurement System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Topology
          2. 10.2.1.2.2 RTD Selection
          3. 10.2.1.2.3 Excitation Current
          4. 10.2.1.2.4 Reference Resistor RREF
          5. 10.2.1.2.5 PGA Setting
          6. 10.2.1.2.6 Common-Mode Input Range
          7. 10.2.1.2.7 Input and Reference Low-Pass Filters
          8. 10.2.1.2.8 Register Settings
        3. 10.2.1.3 Application Curves
      2. 10.2.2 K-Type Thermocouple Measurement (-200°C to +1250°C) with Cold-Junction Compensation
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Biasing Resistors
          2. 10.2.2.2.2 Input Filtering
          3. 10.2.2.2.3 PGA Setting
          4. 10.2.2.2.4 Cold-Junction Measurement
          5. 10.2.2.2.5 Calculated Resolution
          6. 10.2.2.2.6 Register Settings
    3. 10.3 Do's and Don'ts
  11. 11Power-Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

8 Parameter Measurement Information

8.1 Noise Performance

The ADC noise performance is optimized by adjusting the data rate and PGA setting. Generally, the lowest input-referred noise is achieved using the highest gain possible, consistent with the input signal range. Do not set the gain too high or the result is ADC overrange. Noise also depends on the output data rate. As the data rate reduces, the ADC bandwidth correspondingly reduces. This reduction in total bandwidth results in lower overall noise. Table 1 to Table 6 summarize the noise performance of the device. The data are representative of typical noise performance at TA = 25°C. The data shown are the result of averaging the readings from multiple devices and were measured with the inputs shorted together. A minimum of 128 consecutive readings were used to calculate the root mean square (RMS) and peak-to-peak (PP) noise for each reading.

Table 1, Table 3, and Table 5 list the input-referred noise in units of μVRMS and μVPP for the conditions shown. Table 2, Table 4, and Table 6 list the corresponding data in units of ENOB (effective number of bits) where ENOB for the RMS noise is defined as in Equation 1:

Equation 1. ENOB = ln((2 · VREF/Gain) / VNRMS) / ln(2)

where

ENOB for the peak-to-peak noise is calculated with the same method.

Table 3 to Table 6 use the internal reference available on the ADS1247 and ADS1248. The data are also representative of the ADS1246 noise performance when using a low-noise external reference such as the REF5025 or the REF5020.

Table 1. Noise in μVRMS and (μVPP)
at AVDD = 5 V, AVSS = 0 V, and External Reference = 2.5 V

DATA RATE
(SPS)		 PGA SETTING
1 2 4 8 16 32 64 128
5 1.1 (4.99) 0.68 (3.8) 0.37 (1.9) 0.19 (0.98) 0.1 (0.44) 0.07 (0.31) 0.05 (0.27) 0.05 (0.21)
10 1.53 (8.82) 0.82 (3.71) 0.5 (2.69) 0.27 (1.33) 0.15 (0.67) 0.08 (0.5) 0.06 (0.36) 0.07 (0.34)
20 2.32 (13.37) 1.23 (6.69) 0.71 (3.83) 0.34 (1.9) 0.18 (1.01) 0.12 (0.71) 0.10 (0.51) 0.09 (0.54)
40 2.72 (17.35) 1.33 (7.65) 0.68 (3.83) 0.38 (2.21) 0.22 (1.13) 0.14 (0.77) 0.15 (0.78) 0.14 (0.76)
80 3.56 (22.67) 1.87 (12.3) 0.81 (5.27) 0.5 (3.49) 0.3 (1.99) 0.19 (1.24) 0.19 (1.16) 0.18 (1.04)
160 5.26 (42.03) 2.52 (17.57) 1.32 (9.22) 0.67 (5.25) 0.41 (2.89) 0.26 (1.91) 0.27 (1.74) 0.26 (1.74)
320 9.39 (74.91) 4.68 (39.48) 2.69 (18.95) 1.24 (9.94) 0.68 (5.25) 0.45 (3.08) 0.38 (2.71) 0.36 (2.46)
640 13.21 (119.66) 6.93 (59.31) 3.59 (28.55) 1.53 (10.68) 0.95 (8.7) 0.63 (4.94) 0.53 (3.74) 0.5 (3.55)
1000 32.34 (443.91) 16.11 (185.67) 11.54 (92.23) 4.65 (37.55) 2.02 (23.14) 1.15 (12.29) 0.77 (7.42) 0.64 (4.98)
2000 32.29 (372.54) 15.99 (182.27) 8.02 (91.73) 4.08 (45.89) 2.19 (24.14) 1.36 (12.32) 1.08 (8.03) 1.0 (6.93)

Table 2. Effective Number of Bits from RMS Noise and (Peak-to-Peak Noise)
at AVDD = 5 V, AVSS = 0 V, and External Reference = 2.5 V

DATA RATE
(SPS)		 PGA SETTING
1 2 4 8 16 32 64 128
5 22.1 (19.9) 21.8 (19.3) 21.7 (19.3) 21.6 (19.3) 21.6 (19.4) 21.1 (18.9) 20.6 (18.1) 19.6 (17.5)
10 21.6 (19.1) 21.5 (19.4) 21.3 (18.8) 21.1 (18.8) 21 (18.8) 20.9 (18.3) 20.3 (17.7) 19.1 (16.8)
20 21 (18.5) 21 (18.5) 20.7 (18.3) 20.8 (18.3) 20.7 (18.2) 20.3 (17.7) 19.6 (17.2) 18.7 (16.1)
40 20.8 (18.1) 20.8 (18.3) 20.8 (18.3) 20.6 (18.1) 20.4 (18.1) 20.1 (17.6) 19 (16.6) 18.1 (15.6)
80 20.4 (17.8) 20.4 (17.6) 20.6 (17.9) 20.3 (17.5) 20 (17.3) 19.6 (16.9) 18.6 (16) 17.7 (15.2)
160 19.9 (16.9) 19.9 (17.1) 19.9 (17) 19.8 (16.9) 19.5 (16.7) 19.2 (16.3) 18.1 (15.5) 17.2 (14.5)
320 19 (16) 19 (16) 18.8 (16) 18.9 (15.9) 18.8 (15.9) 18.4 (15.6) 17.6 (14.8) 16.7 (14)
640 18.5 (15.4) 18.5 (15.4) 18.4 (15.4) 18.6 (15.8) 18.3 (15.1) 17.9 (14.9) 17.2 (14.4) 16.3 (13.4)
1000 17.2 (13.5) 17.2 (13.7) 16.7 (13.7) 17 (14) 17.2 (13.7) 17.1 (13.6) 16.6 (13.4) 15.9 (12.9)
2000 17.2 (13.7) 17.3 (13.7) 17.2 (13.7) 17.2 (13.7) 17.1 (13.7) 16.8 (13.6) 16.1 (13.2) 15.3 (12.5)

Table 3. Noise in μVRMS and (μVPP)
at AVDD = 5 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 PGA SETTING
1 2 4 8 16 32 64 128
5 1.35 (7.78) 0.7 (4.17) 0.35 (2.03) 0.17 (0.95) 0.1 (0.53) 0.06 (0.32) 0.05 (0.31) 0.05 (0.29)
10 1.8 (10.82) 0.88 (5.26) 0.5 (2.75) 0.24 (1.47) 0.13 (0.8) 0.09 (0.49) 0.07 (0.39) 0.07 (0.4)
20 2.62 (14.32) 1.22 (7.05) 0.66 (3.88) 0.35 (2.05) 0.19 (1.09) 0.12 (0.66) 0.1 (0.61) 0.1 (0.55)
40 2.64 (16.29) 1.34 (7.75) 0.69 (4.06) 0.35 (2.07) 0.21 (1.15) 0.15 (0.85) 0.14 (0.81) 0.13 (0.75)
80 3.69 (23.62) 1.82 (10.81) 0.89 (5.48) 0.51 (2.68) 0.3 (1.69) 0.21 (1.32) 0.2 (1.09) 0.18 (0.98)
160 5.7 (35.74) 2.63 (16.9) 1.34 (8.82) 0.68 (4.24) 0.4 (2.65) 0.3 (1.92) 0.28 (1.88) 0.26 (1.57)
320 9.67 (67.44) 4.95 (35.3) 2.59 (17.52) 1.29 (8.86) 0.72 (4.35) 0.49 (3.03) 0.4 (2.44) 0.37 (2.34)
640 13.66 (93.06) 7.04 (45.2) 3.63 (18.73) 1.84 (12.97) 1.02 (6.51) 0.68 (4.2) 0.58 (3.69) 0.53 (3.5)
1000 31.18 (284.59) 16 (129.77) 7.58 (61.3) 3.98 (33.04) 2.08 (16.82) 1.16 (9.08) 0.83 (5.42) 0.68 (4.65)
2000 31.42 (273.39) 15.45 (130.68) 8.07 (67.13) 4.06 (36.16) 2.29 (19.22) 1.38 (9.87) 1.06 (6.93) 1.0 (6.48)

Table 4. Effective Number of Bits from RMS Noise and (Peak-to-Peak Noise)
at AVDD = 5 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 PGA SETTING
1 2 4 8 16 32 64 128
5 21.5 (19) 21.5 (18.9) 21.5 (18.9) 21.5 (19) 21.3 (18.9) 21 (18.6) 20.2 (17.7) 19.2 (16.8)
10 21.1 (18.5) 21.1 (18.6) 21 (18.4) 21 (18.4) 20.9 (18.3) 20.5 (18) 19.8 (17.3) 18.7 (16.3)
20 20.6 (18.1) 20.7 (18.1) 20.6 (18) 20.5 (17.9) 20.4 (17.8) 20.1 (17.6) 19.2 (16.7) 18.3 (15.8)
40 20.6 (17.9) 20.5 (18) 20.5 (17.9) 20.5 (17.9) 20.2 (17.8) 19.7 (17.2) 18.8 (16.3) 17.9 (15.4)
80 20.1 (17.4) 20.1 (17.5) 20.1 (17.5) 20 (17.5) 19.7 (17.2) 19.2 (16.6) 18.3 (15.8) 17.5 (15)
160 19.5 (16.8) 19.6 (16.9) 19.5 (16.8) 19.5 (16.9) 19.3 (16.6) 18.7 (16) 17.8 (15.1) 16.9 (14.3)
320 18.7 (15.9) 18.7 (15.8) 18.6 (15.8) 18.6 (15.8) 18.4 (15.8) 18 (15.4) 17.3 (14.7) 16.4 (13.7)
640 18.2 (15.4) 18.1 (15.5) 18.1 (15.7) 18.1 (15.3) 17.9 (15.3) 17.5 (14.9) 16.8 (14.1) 15.9 (13.2)
1000 17 (13.8) 17 (13.9) 17 (14) 17 (13.9) 16.9 (13.9) 16.8 (13.8) 16.2 (13.5) 15.5 (12.7)
2000 17 (13.9) 17 (13.9) 17 (13.9) 16.9 (13.8) 16.8 (13.7) 16.5 (13.7) 15.9 (13.2) 15 (12.3)

Table 5. Noise in μVRMS and (μVPP)
at AVDD = 3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 PGA SETTING
1 2 4 8 16 32 64 128
5 2.5 (14.24) 1.32 (6.92) 0.67 (3.48) 0.32 (1.68) 0.17 (0.9) 0.09 (0.51) 0.08 (0.42) 0.07 (0.39)
10 3.09 (16.85) 1.69 (9.32) 0.82 (4.68) 0.42 (2.41) 0.23 (1.18) 0.11 (0.63) 0.11 (0.66) 0.1 (0.55)
20 4.55 (24.74) 2.19 (12.82) 1.07 (5.94) 0.55 (3.38) 0.28 (1.66) 0.16 (1.0) 0.15 (0.92) 0.14 (0.87)
40 5.06 (34.59) 2.39 (14.49) 1.27 (7.75) 0.66 (4.01) 0.36 (2.18) 0.21 (1.16) 0.21 (1.27) 0.15 (0.84)
80 6.63 (43.46) 3.28 (20.22) 1.79 (10.64) 0.89 (5.48) 0.47 (2.95) 0.29 (1.63) 0.28 (1.64) 0.21 (1.24)
160 9.75 (68.28) 4.89 (32.19) 2.36 (17.74) 1.26 (9.87) 0.65 (4.77) 0.4 (2.6) 0.4 (2.7) 0.3 (2.12)
320 19.22 (140.06) 9.8 (82.24) 4.81 (32.74) 2.47 (18.59) 1.27 (9.45) 0.71 (5.83) 0.5 (3.36) 0.43 (2.86)
640 27.07 (192.96) 13.54 (100.26) 6.88 (49.07) 3.4 (25.93) 1.76 (12.49) 1.02 (7.49) 0.71 (4.81) 0.6 (4.06)
1000 40.83 (388.28) 20.39 (185.96) 10.39 (89.38) 5.09 (43.28) 2.66 (22.78) 1.45 (11.01) 0.93 (6.74) 0.74 (4.86)
2000 42.06 (322.85) 21.15 (166.75) 10.66 (92.68) 5.61 (44.08) 2.92 (23.06) 1.68 (11.71) 1.19 (8.23) 1.05 (6.97)

Table 6. Effective Number of Bits from RMS and (Peak-to-Peak Noise)
at AVDD = 3 V, AVSS = 0 V, and Internal Reference = 2.048 V

DATA RATE
(SPS)		 PGA SETTING
1 2 4 8 16 32 64 128
5 20.6 (18.1) 20.6 (18.2) 20.5 (18.2) 20.6 (18.2) 20.5 (18.1) 20.4 (17.9) 19.6 (17.2) 18.8 (16.3)
10 20.3 (17.9) 20.2 (17.7) 20.3 (17.7) 20.2 (17.7) 20.1 (17.7) 20.1 (17.6) 19.1 (16.6) 18.3 (15.8)
20 19.8 (17.3) 19.8 (17.3) 19.9 (17.4) 19.8 (17.2) 19.8 (17.2) 19.6 (17) 18.7 (16.1) 17.8 (15.2)
40 19.6 (16.9) 19.7 (17.1) 19.6 (17.0) 19.6 (17) 19.5 (16.8) 19.2 (16.8) 18.2 (15.6) 17.7 (15.2)
80 19.2 (16.5) 19.3 (16.6) 19.1 (16.6) 19.1 (16.5) 19 (16.4) 18.7 (16.3) 17.8 (15.3) 17.2 (14.7)
160 18.7 (15.9) 18.7 (16) 18.7 (15.8) 18.6 (15.7) 18.6 (15.7) 18.3 (15.6) 17.3 (14.5) 16.7 (13.9)
320 17.7 (14.8) 17.7 (14.6) 17.7 (14.9) 17.7 (14.7) 17.6 (14.7) 17.5 (14.4) 17 (14.2) 16.2 (13.4)
640 17.2 (14.4) 17.2 (14.3) 17.2 (14.3) 17.2 (14.3) 17.1 (14.3) 16.9 (14.1) 16.5 (13.7) 15.7 (12.9)
1000 16.6 (13.4) 16.6 (13.4) 16.6 (13.5) 16.6 (13.5) 16.6 (13.5) 16.4 (13.5) 16.1 (13.2) 15.4 (12.7)
2000 16.6 (13.6) 16.6 (13.6) 16.6 (13.4) 16.5 (13.5) 16.4 (13.4) 16.2 (13.4) 15.7 (12.9) 14.9 (12.2)