8.6.15 ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0]
ALERT_CH_SEL is shown in Figure 52 and described in Table 29.
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Figure 52. ALERT_CH_SEL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
ALERT_CH_SEL[7:0] |
R/W-0b |
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Table 29. ALERT_CH_SEL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
ALERT_CH_SEL[7:0] |
R/W |
0b |
Select channels for which the alert flags can assert the ALERT pin.
0b = Alert flags for this channel do not assert the ALERT pin.
1b = Alert flags for this channel assert the ALERT pin.
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