8.6.28 EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0]
EVENT_COUNT_CH1 is shown in Figure 65 and described in Table 42.
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Figure 65. EVENT_COUNT_CH1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
LOW_THRESHOLD_CH1_LSB[3:0] |
EVENT_COUNT_CH1[3:0] |
R/W-0b |
R/W-0b |
|
Table 42. EVENT_COUNT_CH1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-4 |
LOW_THRESHOLD_CH1_LSB[3:0] |
R/W |
0b |
Lower 4-bits of low threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. |
3-0 |
EVENT_COUNT_CH1[3:0] |
R/W |
0b |
Configuration for checking 'n+1' consecutive samples above threshold before setting event flag. |