8.6.45 LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0]
LOW_TH_CH5 is shown in Figure 82 and described in Table 59.
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Figure 82. LOW_TH_CH5 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
LOW_THRESHOLD_CH5_MSB[7:0] |
R/W-0b |
|
Table 59. LOW_TH_CH5 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
LOW_THRESHOLD_CH5_MSB[7:0] |
R/W |
0b |
MSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result. |