A common design goal in a battery-powered application is reducing power consumption of the analog signal chain, typically consisting of a sensor, an amplifier, and an analog-to-digital converter (ADC). Sensors can be left always on because of their longer latencies at power-up. For ADCs, the power consumption is often dominated by the conversion cycle and it is common to operate ADC in burst mode to facilitate a shorter conversion cycle to lower power consumption. Now there are two amplifier choices for reducing the power consumption, these amplifiers are discussed in detail in this document.

The primary choice usually is to select an amplifier with lower quiescent current (power) and keep the amplifier on during the entire ADC acquisition and conversion cycles. While this can look attractive at first, the main trade-off here is that these low-power amplifiers tend to have a higher thermal noise floor and higher output impedance which affects precision and output drive, respectively. Table 1 shows the typical data for some low-power amplifiers.

As Table 1 shows, the lower the quiescent current of an amplifier, the higher is the thermal noise floor. This higher thermal noise can be acceptable if the signal frequency is well under 100 Hz as the low-frequency noise of these amplifiers becomes more dominant than the thermal noise floor. If the signal frequency is higher than 1 kHz, a slightly better secondary choice is to use an amplifier with a lower thermal noise floor and shutdown functionality to improve signal-to-noise ratio as well as maintain lower power. The lower power can be achieved by periodically enabling the amplifier to make a measurement, when required, while disabling the amplifier for the remainder of the time. The amplifier must be enabled just before the end of the ADC acquisition cycle to get a settled signal in time for the beginning of the ADC conversion cycle. This technique of using shutdown amplifiers to make periodic measurements is referred to as duty-cycling.

The quiescent current of an amplifier in enable, disable modes and the enable, disable times are the key specifications that dictate the average power consumption when duty-cycling an amplifier. Table 2 shows that the enable time of these shutdown amplifiers is inversely proportional to the bandwidth. The OPA310S is a clear exception to the trend. This device achieves a much lower enable time of 1 μs at a 3-MHz bandwidth while consuming lower quiescent current of 165 μA when enabled and 265 nA when disabled. Along with lower thermal noise floor of 13 nV / √Hz, this makes the OPAx310S an excellent choice for systems implementing duty-cycling techniques for power savings.

For higher power savings, it is important to lower the amplifier ON time which consequently reduces the duty cycle (%) to lower the average quiescent current. The lower average quiescent current directly lowers energy consumption leading to a longer battery life. Table 3 summarizes the minimum duty-cycle values that can be achieved with these amplifiers assuming a measurement must be taken every 1 ms with 0.01% accuracy. The total ON time of the amplifier is the summation of the time it takes to turn on the amplifier and the time it takes for the output to settle to ADC accuracy (assumed to be 0.01% in this case).

Equation 1 through Equation 3 describe the total ON time, total OFF time, and minimum duty cycle (D).

The OPA310S (which has faster enable time and settling time) helps to achieve an overall lower total ON time leading to shorter duty cycle in comparison to other duty-cycled amplifiers. Table 4 outlines the average current consumption while meeting the 0.01% settling time requirements across 1-ms time frame along with the thermal noise floor, which is the performance parameter.

In comparison to the duty-cycled TLV9061, the OPA310S achieves 89% lower quiescent current for just 3 nV / √Hz of increase in the thermal noise floor. In comparison to the always on TLV8541, the OPA310S achieves 95% lower noise for just 0.19 μA increase in the average quiescent current. These improvements make the OPAx310S family a good fit for power-conscious applications that require a certain degree of noise performance. These comparisons above are for static power consumption because the dynamic power consumption can vary depending on the amplifier output load in an application. The above comparisons hold true as long as the dynamic power consumption is smaller when compared to static power consumption.

The OPAx310S devices also offer better reliability and avoid faults or failures when interfacing to sensors. These sensors commonly require a different power-supply voltage in comparison to the amplifier, thus mandating a careful power sequencing. If done incorrectly, this potentially leads to sensor loading at the input of the amplifier and faulty signals at the output of the amplifier. This is where the fail-safe input ESD structure of the OPAx310S can help in comparison to the traditional input ESD structure of most amplifiers which is shown in Figure 1.

An amplifier with a traditional input ESD structure has ESD protection diodes from inputs to the positive rail. With this structure, any input signal presenting from the sensor before the presence of the power supply of the amplifier can potentially turn on and forward bias the ESD protection diode between the IN and V+ pins. This, in turn, leads to the sensor output voltage acting as a power-supply voltage and providing quiescent current for the amplifier (also called back powering). This can cause heavy loading of the sensor at the amplifier input and subsequently produce a fault signal at the amplifier output.

The OPAx310S is different from the TLV90xxS in that the OPAx310S does not have any protection ESD diodes from the IN to the V+ pins. During power sequencing, this avoids possible sensor loading at the amplifier input and a possible fault signal at the amplifier output. In fact, the OPAx310S inputs when driven by sensor can go as high as 6 V from V– regardless of what the voltage is on the V+ pin. Further, the OPAx310S device achieves a robust ESD performance of 8-kV HBM (Human body model) and 1.5-kV CDM (Charged-device model) with these fail-safe inputs.

A detailed set of measurements of this robust behavior is found in the Op Amp ESD Protection Structures application report. Thus, the fast enable time paired with the fail-safe ESD structure of the OPAx310S family makes the devices a great choice to pair with the high-output impedance sensors and burst mode ADCs. The OPAx310S family is available in single, dual, and quad channels with and without shutdown. Table 5 shows the device options with the shutdown feature included.