SBAU352 June   2020 ADS131B04-Q1

 

  1.   ADS131B04-Q1 Evaluation Module
    1.     Trademarks
    2. 1 EVM Overview
      1. 1.1 ADS131B04-Q1EVM Kit
      2. 1.2 ADS131B04-Q1EVM Board
    3. 2 EVM Analog Interface
      1. 2.1 ADC Analog Input Signal Path
      2. 2.2 ADC External Clock (CLKIN) Options
    4. 3 Digital Interface
      1. 3.1 SPI Communication
      2. 3.2 Connection to the PHI
      3. 3.3 Digital Header
      4. 3.4 LaunchPad Connectors
    5. 4 Power Supplies
    6. 5 ADS131B04-Q1EVM Initial Setup
      1. 5.1 Default Jumper Settings
      2. 5.2 EVM Graphical User Interface (GUI) Software Installation
    7. 6 ADS131B04-Q1EVM Operation
      1. 6.1 EVM GUI Global Settings for ADC Control
      2. 6.2 Register Map Configuration Tool
      3. 6.3 Time Domain Display Tool
      4. 6.4 Spectral Analysis Tool
      5. 6.5 Histogram Tool
    8. 7 ADS131B04-Q1EVM Bill of Materials, PCB Layout, and Schematic
      1. 7.1 Bill of Materials
      2. 7.2 PCB Layout
      3. 7.3 Schematic

2.2 ADC External Clock (CLKIN) Options

The ADS131B04-Q1 requires a continuous, free-running external master clock at the CLKIN pin for normal operation. The onboard complementary metal oxide semiconductor (CMOS) crystal oscillator (Y1) provides the nominal 8.192-MHz clock frequency used in the high-resolution (HR) mode of the device. Two D flip-flops (U3) divide the Y1 clock output to produce clock frequencies of 4.096 MHz and 2.048 MHz to support the low-power (LP) mode and very-low-power (VLP) mode, respectively.

Install a jumper in the appropriate position on the JP6 header shown in Figure 4 to provide selectable clock frequency options. An external clock frequency can also be provided to any even-numbered pin on JP6 when the jumper is uninstalled. TI also recommends powering down Y1 by installing JP5 when providing an external clock. When using an external clock, ground must be shared between the external clock source and the EVM ground. The external clock must adhere to the frequency and amplitude limits outlined in the ADS131B04-Q1 data sheet. Table 4 lists the JP6 jumper settings for the clock input selections.

In addition to jumper settings, each of the power modes requires configuration register settings outlined in Section 6.1.

clkin_sbau332.gifFigure 4. CLKIN External Clock (PCB)

Table 4. CLKIN External Clock Options

J13 Jumper Setting Clock Frequency Description
[1-2] 8.192 MHz Nominal clock for high-resolution mode (default)
[3-4] 4.096 MHz Nominal clock for low-power mode
[5-6] 2.048 MHz Nominal clock for very-low-power mode