SBAU374A May   2021  – May 2022 DAC12DL3200

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Low Latency Evaluation of Receive and Transmit
    2. 1.2 Related Documentation
      1.      Technical Reference Documents
      2.      TSW14DL3200EVM and ADC12DL3200EVM Operation
  4. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  5. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the DAC12DL3200EVM and TSW14DL3200EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (*RF Outputs Disabled Until Directed)
      1. 3.5.1 If External Clocking is Used (Optional)
    6. 3.6  Turn On the TSW14DL3200EVM 12-V Power and Connect to the PC
    7. 3.7  Turn On the DAC12DL3200EVM 5-V Power Supply and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the DAC12DL3200EVM GUI and Program the DAC and Clocks for Single Channel, NRZ Mode 2 Operation
    10. 3.10 Open the HSDC Software and Load the FPGA Image to the TSW14DL3200EVM
    11. 3.11 DxSTRB Timing Adjustment
  6. 4Other Modes of Operation
    1. 4.1 Single-Channel RF Mode 2 (2nd Nyquist Zone)
    2. 4.2 Dual-Channel Output Mode 0
    3. 4.3 Dual Channel Mode1 Setup
    4. 4.4 Dual-Channel 2xRF Mode 0 DAC Setup
    5. 4.5 Direct Digital Synthesis Mode
  7. 5Register Log File
  8. 6Device Configuration
    1. 6.1 Tab Organization
    2. 6.2 Low-Level Control
  9.   A Troubleshooting the DAC12DL3200EVM
  10.   B DAC12DL3200EVM Onboard Clocking Configuration

4.2 Dual-Channel Output Mode 0

Complete the following steps to work in dual-channel output mode 0:

  1. Change the frequency of the signal generator connected to EXT_DACCLK (SMA J2) to 3.2 GHz.
  2. Select the DAC RESET switch.
  3. Click on the DAC12DL3200EVM Low Level View tab.
  4. Click on the File icon and navigate to “EXT_CLK_Mode0_NRZ_Dual_DAC.cfg” and click the OK button to load the LMK and DAC registers.

    This configuration file will setup the DAC to operate in dual-channel mode with outputs available on CHA and CHB.

  5. In the HSDC Pro GUI, in the device drop-down menu, select "DAC12DL3200_MODE0_12b_sync_istrb”. If the firmware is already loaded, skip the next step.
  6. When prompted, click the Yes button to update the firmware. After the firmware is downloaded, do the DxSTR register write mentioned in the DxSTRB Timing Adjustment section.
  7. Enter "3.2GHz" for the Data Rate.
  8. In the I/Q Multitone Generator window in the lower left of the GUI, enter the following parameters: # of tones "1", tone center "1GHz" then click the Create Tones button.
  9. Click the Send button in the upper left of the main GUI page to send the test tone to the DAC EVM. There should now be a 1-GHz output tone on CHA SMA connector J1 and CHB SMA connector J4.