SBAU395 april   2023 DAC39RF10

 

  1.   Introduction
  2. 1Trademarks
  3. 2Required Equipment
  4. 3Setup Procedure
    1. 3.1  Installing the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Installing the DAC39RF10EVM Configuration GUI Software
    3. 3.3  Connect the DAC39RF10EVM and TSW14J59EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Spectrum Analyzer to the EVM
    6. 3.6  Turn On the TSW14J59EVM Power and Connect to the PC
    7. 3.7  Turn On the DAC39RF10EVM Power Supplies and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Launch the DAC39RF10EVM GUI and Program the DAC EVM
    10. 3.10 Programming the NCO
      1. 3.10.1 SPIDAC( NCO only) Operation
    11. 3.11 Launch the HSDCpro Software and Load the FPGA Image to the TSW14J59EVM
  5. 4Device Configuration
    1. 4.1 Supported JESD204C Device Features
    2. 4.2 Tab Organization
    3. 4.3 Register Map and Console Control
  6. 5Troubleshooting the DAC39RF10EVM
  7. 6References
    1. 6.1 Technical Reference Documents
    2. 6.2 TSW14J59EVM Operation
  8. 7Appendix
    1. 7.1 Customizing the EVM for Optional Clocking Support
      1. 7.1.1 LMX->DACCLK | LMX/LMK-> FPGA option (Default)
      2. 7.1.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
      3. 7.1.3 EXT->DACCLK | LMK-> FPGA Clocking Option
    2. 7.2 Signal Routing
    3. 7.3 Analog Outputs
    4. 7.4 Jumpers and LEDs

3.5 Connect the Spectrum Analyzer to the EVM

Connect a spectrum analyzer to the Aoutp (J13) SMA connector of the DAC39RF10EVM .

When LMX->DACCLK | LMX/LMK->FPGA Clocking option is Used (Default)

  1. Connect a signal generator to the LMX CLKp input of the EVM. This signal generator must be a low-noise signal generator. Configure the signal generator for the desired clock frequency in the range of 0.8 to 10.24 GHz (for this example 10.24 GHz is used). For best performance when using an RF signal generator, the power input to the LMX CLKp SMA connector must be 8-10 dBm (2 Vpp into 50 Ω).
  2. This step is only need if third clocking option(EXT-> DACLK | LMK->FPGA) is used otherwise skip to next step. Connect a signal generator to the LMK CLKp input of the EVM at SMA (J5). This signal is used to generate the necessary FPGA clock signal. Configure the signal generator for the desired (160 MHz) clock frequency. Set the output power to approximately 5–7 dBm.
    Note:
    1. The FPGA REF clock frequency can be obtained from the DAC39RF10EVM GUI. Once the DAC39RF10EVM GUI is configured to the desired JMODE mode and clock rate. The Reference Clock frequency required by the EVM is displayed on first page of the GUI shown in Configuration of DAC39RF10EVM GUI
    2. Make sure that the DEVCLK and Reference clock sources are frequency-locked using a common 10-MHz reference to for functionality.
    3. Do not turn on the RF output of any signal generator at this time.