The DAC39RF10EVM can be configured to use EXT->DACCLK | LMK-> FPGA Clocking option. In this use case, the user provide a two clock signal. A high frequency(10-15dBm) signal to an SMA labeled LMX CLKp. This signal is routed though the splitter to Balun and LMX1204. The Balun converts the single ended signal into differential and is used to clock the DAC. The second low frequency signal is CLKIN1 input of LMK04828. The LMK04828 is used to generates the low frequency DAC SYSERF signal, FPGA reference clocks and FPGA SYSREF signal. The LMK04828 is used in clock distribution mode and provides several copies/divided down version of FPGA reference clock and FPGA SYSREF signalFigure 7-3 shows the block diagram of external reference clocking option:

The EVM can be configured to use external reference clocking option with the following steps:

• Remove C141 and C142, populate C136 and C139
• Remove C138 and C140, populate C134 and C135
• Remove C65 and R64, populate C64 and R66
• Remove C73 and C74, populate C75 and C76

Figure 7-3 External Reference Clocking System Block Diagram