The transformer output is connected to two rectification diodes (D1 and D2) to provide the main high-side supply voltage (VADC_HV). JP2 and JP3 connect VADC_HV to the ADC APWR and DPWR supply pins, respectively. The ADS131B26-Q1 uses two internal LDOs to generate the primary analog and digital supplies (AVDD and IOVDD). Series 0.1-ohm resistors (R57 and R66) are provided for LDO supply current measurements and are not required by the ADC for normal operation. When JP2 and JP3 are installed in the [2-3] position, VADC_HV is nominally approximately 5.1 V. To evaluate the ADS131B26-Q1 with an external APWR and DPWR supply, uninstall the jumpers on JP2 and JP3 and connect the external supply to the corresponding terminal block inputs (J6 and J8). Alternatively, the ADC internal LDOs can be completely bypassed by moving both JP2 and JP3 jumpers to the [1-2] position. In this configuration, APWR must be between 3 V and 3.6 V, and DPWR must be between 3 V and 5.5 V. Figure 4-2 shows the analog and digital ADC supply options.

Figure 4-2 ADC Analog and Digital Supply Options (Schematic)