SBAU436A January   2024  – February 2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Analog Input Options
      1. 2.1.1 Differential SMA Inputs
      2. 2.1.2 Single-Ended SMA Inputs
      3. 2.1.3 Differential Input Pins
    2. 2.2 Power Supplies
    3. 2.3 ADC Connections and Decoupling
    4. 2.4 ADC Input Amplifiers
    5. 2.5 VCOM Buffer
    6. 2.6 Voltage Reference
    7. 2.7 Clock Tree
    8. 2.8 Digital Interfaces
  9. 3Software
    1. 3.1 ADS1278EVM Software Installation
  10. 4Implementation Results
    1. 4.1 Hardware Connections
    2. 4.2 Optional EVM Configuration
    3. 4.3 GUI Settings for ADC Control
    4. 4.4 Time Domain Display
    5. 4.5 Frequency Domain Display
    6. 4.6 Histogram Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7References
  14. 8Revision History

4.1 Hardware Connections

Connect the EVM as shown in Figure 5-1 after installing the software:

  1. Physically connect P2 of the PHI to J5 of the ADS1278 EVM.
  2. Install the screws to provide a robust connection. Connect the USB on the PHI to the computer.
    1. LED D5 on the PHI lights up, indicating that the PHI is powered up.
    2. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with the PC.
  3. Power the ADS1278 EVM through the J10 terminal with 6V.
  4. Start the software GUI. Notice that the LEDs on the PHI blink slowly when the FPGA firmware is loaded on the PHI. Loading takes a few seconds.
  5. Connect the signal generator. The input range is 0V to 5V. A common input is a 4.9VPP signal with a 2.5V offset. This signal is adjusted just below the full-scale range to avoid clipping.
GUID-20231113-SS0I-NMLQ-GW9G-XBSJJJ9PGPVB-low.svgFigure 4-1 Hardware Connections