SBAU447 May   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Coupon Locations and Descriptions
    2. 2.2 EVM Assembly Instructions
    3. 2.3 Interfaces
      1. 2.3.1 Analog Input
      2. 2.3.2 Amplifier Output
        1. 2.3.2.1 Differential Output
        2. 2.3.2.2 Single-Ended Output, Fixed Gain
        3. 2.3.2.3 Single-Ended Output, Ratiometric Gain
      3. 2.3.3 Modulator Output
        1. 2.3.3.1 Internal Clock
        2. 2.3.3.2 External Clock
    4. 2.4 Power Supplies
      1. 2.4.1 VDD1/AVDD Input
      2. 2.4.2 VDD2/DVDD Input
    5. 2.5 EVM Operation
      1. 2.5.1 Analog Input and VDD1/AVDD Power
      2. 2.5.2 Outputs and VDD2/DVDD Power
      3. 2.5.3 Test Procedure
        1. 2.5.3.1 Equipment Setup
        2. 2.5.3.2 Procedure
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.3.2.3 Single-Ended Output, Ratiometric Gain

DIYAMC-0-EVM Single-Ended Output, Ratiometric Gain CircuitFigure 2-5 Single-Ended Output, Ratiometric Gain Circuit

Figure 3-5 shows the example single-ended output with ratiometric gain output circuit for the DIYAMC-0-EVM.

Row 3 of the EVM provides a single-ended analog output with ratiometric gain. Using Coupon A3 as an example, the output is accessible to the user by connector J6. The passive components of the output are comprised of R10, R12, C26, and C27 to form two RC filters. The output filter from pin 6 of the device has a cutoff frequency of 159MHz. C21 and C22 serve as decoupling capacitors for noise reduction and low-side supply (VDD2) stability.

Using an oscilloscope, the user can observe the output signal at J6.2 (VO). This trace includes a 0 Ohm resistor, R9, which can be removed to apply an external reference to J6.3 (REF). When a reference voltage is applied, the output ranges from 0 to REF centered at REF/2. This is filtered through R12 and C27. VDD2 is extended to pin 6 of the device to J6.3 (REF). Pin 7 of the device functions as the device’s output. This is filtered through R10 and C26.