SBAU447 May   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Coupon Locations and Descriptions
    2. 2.2 EVM Assembly Instructions
    3. 2.3 Interfaces
      1. 2.3.1 Analog Input
      2. 2.3.2 Amplifier Output
        1. 2.3.2.1 Differential Output
        2. 2.3.2.2 Single-Ended Output, Fixed Gain
        3. 2.3.2.3 Single-Ended Output, Ratiometric Gain
      3. 2.3.3 Modulator Output
        1. 2.3.3.1 Internal Clock
        2. 2.3.3.2 External Clock
    4. 2.4 Power Supplies
      1. 2.4.1 VDD1/AVDD Input
      2. 2.4.2 VDD2/DVDD Input
    5. 2.5 EVM Operation
      1. 2.5.1 Analog Input and VDD1/AVDD Power
      2. 2.5.2 Outputs and VDD2/DVDD Power
      3. 2.5.3 Test Procedure
        1. 2.5.3.1 Equipment Setup
        2. 2.5.3.2 Procedure
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.3.1 Analog Input

DIYAMC-0-EVM Analog Input Circuit Figure 2-2 Analog Input Circuit

Figure 3-2 shows the example analog input circuit for the DIYAMC-0-EVM.

The input amongst all twenty coupons is identical. Using Coupon A1 as an example, the input is accessible to the user by connector J1. The passive components of the input include R1, R3, & C5 to make a differential anti-aliasing filter with a cutoff frequency of 796kHz, and C7 and C8 to help attenuate common-mode signals. C1 and C2 serve as decoupling capacitors for noise reduction and high-side supply (VDD1) stability.

Using a signal generator or other voltage source, the user can apply an input signal directly to J1.3 (AINP) and J1.2 (AINN). The linear input voltage range of the EVM varies by device selected for the configuration of the user. Reference the device data sheet for more information. Establish the common-mode input voltage if necessary, commonly done by shorting J1.2 (AINN) to J1.1(GND).