SBAU468 September   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Interfaces
      1. 2.1.1 Analog Input
      2. 2.1.2 EVM Output Configurations and Descriptions
      3. 2.1.3 Amplifier Output
        1. 2.1.3.1 Differential Output
        2. 2.1.3.2 Single-Ended Output, Fixed Gain
        3. 2.1.3.3 Single-Ended Output, Ratiometric Gain
      4. 2.1.4 Modulator Output
        1. 2.1.4.1 External Clock
    2. 2.2 Power Supplies
      1. 2.2.1 VDD1/AVDD Input
      2. 2.2.2 VDD2/DVDD Input
    3. 2.3 EVM Operation
      1. 2.3.1 Analog Input and VDD1/AVDD Power
      2. 2.3.2 Outputs and VDD2/DVDD Power
      3. 2.3.3 Test Procedure
        1. 2.3.3.1 Equipment Setup
        2. 2.3.3.2 Procedure
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.1.3.2 Single-Ended Output, Fixed Gain

When using a device with a single-ended output, the J3 connector provides access to the VOUT and VREF output pins of the device.

When R4 is populated and R5 is depopulated, VREF is directly tied to VDD2 and sets the gain for the output. The passive components of R1 and C8 are populated as a low-pass filter to attenuate high frequency noise components. VDD2 and GND2 are accessible through the J2 connector. C5 and C6 serve as decoupling capacitors for VDD2 and help keep the supply stable.

Using an oscilloscope, the user can observe the output signal on J3.2 (VOUT) with respect to J2.1 (GND2).