Design Goals

Design Description

This high-side voltage-to-current (V-I) converter delivers a well-regulated current to a load, R₄. The circuit accepts an input voltage from 0V to 10V and converts it to an output current from 0A to 5A. The current is regulated by feeding the voltage across a low-side, current-sense resistor back to the op amp. The output Darlington pair allows for higher current gain than when using a single, discrete transistor.

Design Notes

1. A resistor divider, formed by R₁ and R₂, is implemented at the input to limit the full-scale voltage at the non-inverting terminal of the amplifier and the output sense resistor (R₅).
2. The high current gain of the Darlington pair reduces the demand on the output current of the op amp.
3. Smaller values of R₄ and R₅ lead to an increased load compliance voltage and a reduction in power dissipated in the full-scale, output state.
4. Feedback components R₃ and C₁ provide frequency compensation to ensure the stability of the circuit during transients. They also help reduce noise. R₃ provides a DC feedback path directly at the current setting resistor, R₅, and C₁ provides a high-frequency feedback path that bypasses the NPN pair.
5. The input bias current will flow through R₃, which will cause a DC error. Therefore, ensure that this error is minimal compared to the offset voltage of the op amp.
6. Select an op amp whose linear output voltage swing includes at least 2 ✕ V_be+V_sense. The output voltage of the op amp will be greater than the voltage at the sense resistor by approximaly double the base-to-emitter voltage, V_be.
7. Use the op amp in its linear operating region, specified under the A_OL test conditions of the data sheet.
8. If needed, an isolation resistor may be placed between the high-frequency feedback path and the base of T1 for stability.

Design Steps

The transfer function of this circuit is provided in the following steps:

1. Using the specifications for the maximum output power dissipation and the maximum output current, determine the maximum value of V_sense.
   $V_{R5\mathrm{Max}}=V_{\mathrm{senseMax}}=\frac{P_{R5\mathrm{Max}}}{I_{\mathrm{oMax}}}=\frac{0.25W}{5A}=50\mathrm{mV}$
2. Calculate the sense resistance, R₅.
   $R_5=\frac{V_{\mathrm{senseMax}}}{I_{\mathrm{oMax}}}=\frac{\mathrm{50mV}}{\mathrm{5A}}=\mathrm{10m\Omega }$
3. Select values for R₁ and R₂ based on the maximum allowable input current, I_iMax, and the desired V_senseMax voltage.
   $R_1=\frac{V_{\mathrm{senseMax}}}{I_{\mathrm{iMax}}}=\frac{\mathrm{50mV}}{\mathrm{200\mu A}}=\mathrm{250\Omega }\approx \mathrm{249\Omega }\mathrm{(Standard\; Value)}$
   $V_{\mathrm{senseMax}}=V_{\mathrm{iMax}}\times \left(\frac{R_2}{R_1+R_2}\right)$
   $R_2=\mathrm{49.6k\Omega }\approx \mathrm{49.9k\Omega \; (Standard\; Value)}$
4. See the Design References section [2] for the design procedure on how to properly size the compensation components, R₃ and C₁.

Design Simulations

DC Simulation Results

Loop Stability Simulation Results

Loop gain phase is 53 degrees.

Compliance Voltage Simulation Results

Design References

1. See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
2. TI Precision Labs

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