3 How the SPICE Model Sets Current Noise

CMOS and JFET devices are often selected for their very low bias current and low current noise. However, in cases where current noise is specified versus frequency you might see the f-squared noise as shown in Figure 2-2. If low current noise was a key requirement in the design, the increased current noise at high frequency can be concerning. It is important to understand that all CMOS and JFET devices will have this effect so some extent, but it might not be specified. Typically, the amplifier model will show the f-squared noise as it is automatically generated when the amplifier voltage noise interacts with the input capacitance. Thus, you can generally use the model to estimate the impact of f-squared noise. Figure 3-1 illustrates a simple op amp model that uses current noise sources, a voltage noise source, input capacitance, and amplifier open loop gain. Note that this model uses current noise sources that are flat across frequency and the f-squared noise occurs as an interaction between the voltage noise source and differential input capacitance. If comparing the current noise simulation to the data sheet noise plot shown in Figure 2-2, shows that they are very similar but the data sheet noise is slightly higher. This can be due to additional sources of f-squared noise inside the device. Thus, in some cases the actual device can have some current noise not included in typical models. Also, the low frequency current noise is from the shot noise of the input leakage current on the ESD structures or any other semiconductor junction ( $\sqrt{2q{I}_b}$ ).

Figure 3-1 OPA350 Simple Noise Model

Figure 3-2 Current Noise vs. Frequency for Simple Noise Model