SBOA590 November   2024 OPA186 , OPA206 , OPA328 , OPA391 , OPA928

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Input Offset Voltage (VOS) Definition
    1. 1.1 Input Offset Voltage Drift (dVOS/dT) Definition
    2. 1.2 VOS and VOS Temperature Drift Inside the Amplifier
    3. 1.3 Laser Trim to Adjust Performance
    4. 1.4 Package Trim (e-Trim™) to Adjust Performance
  5. 2Input bias current (IB) definition
    1. 2.1 Input Bias Current (IB) and IB Temperature Drift Inside the Amplifier
    2. 2.2 Derivation of IB Conversion to VOS
    3. 2.3 Internal Bias Current Cancelation
    4. 2.4 Super Beta Input Transistors
  6. 3Other Factors Influencing Offset
    1. 3.1 Finite Open Loop Gain (AOL)
    2. 3.2 Common Mode Rejection Ratio (CMRR)
    3. 3.3 Power Supply Rejection Ratio (PSRR)
    4. 3.4 AOL, CMRR, and PSRR Over Frequency
    5. 3.5 Electromagnetic Interference Ratio (EMIRR)
    6. 3.6 Mechanical Stress Induced Offset Shift
    7. 3.7 Parasitic Thermocouples
    8. 3.8 Flux Residue and Cleanliness
  7. 4Zero-drift Amplifiers to Minimize VOS and VOS Drift
  8. 5Calibration of VOS, IB, and Gain Error
  9. 6References
  10. 7Revision History

Mechanical Stress Induced Offset Shift

Small amounts of mechanical stress applied to an integrated circuit can cause subtle shifts in operation due to the compression or tension applied to internal components. This stress can be from a flexing of the printed circuit board that the IC is mounted on or even from the soldering process. For op amps, mechanical stress is most often associated with a small shift in VOS. The magnitude of offset shift depends on the amount of mechanical stress applied to the device and the devices susceptibility to stress. The internal op amp design sensitivity to stress can be improved using careful layout methods where the most sensitive internal input transistors are laid out in a symmetrical inter-digitated pattern away from the edges of the die. This symmetrical layout method minimizes the offset shift by maintaining the VBE shift on both input transistors equal (VOS = VBE1 - VBE2 ≌ constant).

The process of soldering an op amp to a printed circuit board may also introduce a shift as large as 100 µV. However, the stresses introduced during the soldering process tend to relax over time and the device eventually returns to an offset near the pre-solder value (e.g. ΔVOS < 10 µV). However, at room temperature this process may take several weeks. One way to accelerate the stress relaxation process is to bake the printed circuit board at high temperature (100°C or greater) after cleaning the board. The baking softens rigidity of the IC package causing a dramatic reduction in the time required to relax the stress.

Aside from the stress introduced by solder reflow, most devices undergo parametric changes over time called long-term shift. These shifts are larger during the initial 1000 hrs of operation than later in the life of the device. Thus, the post clean baking process reduces the initial shift by curing of the molding compound of the device, so that the initial more significant effects are minimized. The long-term shift and soldering related stress effects are also important for voltage reference accuracy, and gain accuracy of instrumentation amplifiers. Long-Term Drift in Voltage References covers the background of long-term shift as well as the bake method to minimize the problem.

Flexing of the printed circuit board may also cause a shift in offset. Thus, the PCB thickness, mounting hardware, and stress introduced by connector tension can all cause shifts in offset performance. Therefore, the mechanical design, enclosure, and connections can all have some impact on electrical performance.