The op amp input pins are connected to the base of the transistors in the differential input pair. The bipolar transistors are current controlled devices, so base current is required to properly bias the input stage (see Section 2.1). The choice of input stage collector current biasing depends on the bandwidth, noise, and slew-rate requirement for the op amp. The base current of the input transistors will be the collector current divided by the current gain of the transistor (β). Thus, the input bias current, I_B, for bipolar devices will depend on the specific product requirements and process technology. Nevertheless, a typical range of uncorrected input bias currents is in hundreds of nano-amps to micro-amps. For some applications, the uncorrected bias current value would introduce large errors that would be considered unacceptable. To solve this issue, the integrated circuit design method bias current cancellation is used to significantly reduce bias current.

The input bias current cancellation is a method where the transistor base current is monitored and an equal but opposite current is summed into the op amp input terminal to cancel the base current (see Figure 2-12). If the cancellation circuit worked perfectly, the input bias current seen from outside of op amp would reduce to zero. However, there is a tolerance in the canceling current so that some residual bias current remains. Typically, the improvement due to input bias current cancellation reduces I_B by a factor of 100. Figure 2-12 shows the bias current reduced from 10 nA to about 1 nA. Also, without bias current cancellation the bias current of bipolar devices always flows in the same direction. For an NPN device, base current flows into the base, and for PNP it flows out of the base. However, when bias current cancellation is used, the residual current after the correction can flow in either direction.

Using bias current cancellation also has an impact on input bias current offset (I_OS). In general, for devices that do not use bias current cancellation the I_B tends to be much larger than I_OS (approximately 10x). This is because the input transistors are well matched. Conversely, when bias current cancellation is used the residual I_B left after the cancellation is an error term, and the two inputs is no longer well matched. Thus, for devices that use bias current cancellation I_B is approximately the same magnitude as I_OS. When I_B >> I_OS, the impact of I_B can be reduced by matching the impedance of the feedback network and non=inverting input of the op amp. Conversely, when I_B ≌ I_OS, matching the impedances no longer helps reduce the effects of I_B and may in fact double the error.

Table 2-2, and Table 2-3 compare a device without I_B cancellation to one with I_B cancellation. Most important notice that the absolute magnitude of I_B is much lower when I_B cancellation is used (-35 nA vs ±4.5 nA). Also, notice that without I_B cancellation I_B >> I_OS, but with cancellation I_B ≈ I_OS. Finally, notice that without I_B cancellation, the polarity of I_B is in one direction, whereas it is in both directions with I_B cancellation (-35 nA vs ±4.5 nA). The negative polarity for I_B without I_B cancellation indicates an PNP input structure.

Figure 2-12 Internal Bias Current Cancellation