SBOA590 November   2024 OPA186 , OPA206 , OPA328 , OPA391 , OPA928

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Input Offset Voltage (VOS) Definition
    1. 1.1 Input Offset Voltage Drift (dVOS/dT) Definition
    2. 1.2 VOS and VOS Temperature Drift Inside the Amplifier
    3. 1.3 Laser Trim to Adjust Performance
    4. 1.4 Package Trim (e-Trim™) to Adjust Performance
  5. 2Input bias current (IB) definition
    1. 2.1 Input Bias Current (IB) and IB Temperature Drift Inside the Amplifier
    2. 2.2 Derivation of IB Conversion to VOS
    3. 2.3 Internal Bias Current Cancelation
    4. 2.4 Super Beta Input Transistors
  6. 3Other Factors Influencing Offset
    1. 3.1 Finite Open Loop Gain (AOL)
    2. 3.2 Common Mode Rejection Ratio (CMRR)
    3. 3.3 Power Supply Rejection Ratio (PSRR)
    4. 3.4 AOL, CMRR, and PSRR Over Frequency
    5. 3.5 Electromagnetic Interference Ratio (EMIRR)
    6. 3.6 Mechanical Stress Induced Offset Shift
    7. 3.7 Parasitic Thermocouples
    8. 3.8 Flux Residue and Cleanliness
  7. 4Zero-drift Amplifiers to Minimize VOS and VOS Drift
  8. 5Calibration of VOS, IB, and Gain Error
  9. 6References
  10. 7Revision History

2 Input bias current (IB) definition

Input bias current (IB) can be modeled as DC current sources on both the inverting and non-inverting input terminals (see Figure 2-1). This bias current develop an error voltage when it flows through the feedback network and source impedance. The error voltage can be referred to the input so that it adds to the VOS and VOS drift error sources. Equation 14 and Equation 15 shows the calculation for converting bias current into an offset voltage. Figure 2-2 and Equation 17 show how the input bias current translates into offset voltage sources.

OPA206 Bias Current Model Figure 2-1 Bias Current Model
Equation 14. V I B P = -   I B P R S
Equation 15. V I B N = I B N ( R F   | |   R G )
Equation 16. ( R F   | |   R G ) = R F R G R F + R G
Equation 17. V I B = I B N ( R F   | |   R G ) - I B P R S
OPA206 Bias Current Translated to Input Offset Voltage Figure 2-2 Bias Current Translated to Input Offset Voltage

The amplifier data sheet normally does not specify the bias current for the inverting and non-inverting input separately, but rather specifies the difference between the bias currents as bias current offset (IOS = IBP - IBN). If the bias currents are equal and the source impedance is equal to the feedback network impedance (RS = RF || RG), then the bias current offset voltages cancel (see Equation 19). However, in most modern precision amplifiers the bias currents have significant offset (IOS ≠ 0). In fact, for most CMOS amplifiers and many bipolar amplifiers the bias currents and bias offset are comparable in magnitude (IB ≈ IOS). Thus, the approach of balancing the source and feedback impedance frequently is not a practical way to minimize input offset voltage due to bias current. When IOS ≥ IB, the best approach to minimizing VIB is by minimizing RS, and RF || RG, not by balancing the source and feedback impedance. Equation 20 shows VIB where IOS is equal on both inputs (IBP = IB + IOS/2, and IBN = IB – IOS/2). The second term in this equation highlights how the IOS effects are not canceled when RS = RF || RG.

Equation 18. I O S = I B P   -   I B N
Equation 19. V I B = I B R F | | R G -   R S ,     f o r   I O S = 0
Equation 20. V I B = I B R F | | R G -   R S + I O S 2 R F | | R G +   R S ,     f o r   I O S   e q u a l   o n   e a c h   i n p u t

Equation 21 and Equation 22 are a good way to estimate the offset voltage due to bias current. These equations assume that half of the bias current offset is equally distributed between the inverting and non-inverting input. The two equations calculate the offset due to IB considering the polarity of the bias current offset (IOS is negative in Equation 21 and positive in Equation 22). For worst case error analysis calculate both values and select the largest absolute value (see Equation 23). Example 1 uses these equations in a calculation for maximum input offset voltage due to bias current for OPA205A.

Equation 21. V I B 1 = I B + I O S 2 ( R F   | |   R G )   -   I B - I O S 2 R S
Equation 22. V I B 2 = I B - I O S 2 ( R F   | |   R G ) -   I B + I O S 2 R S
Equation 23. V I B = m a x ( V I B 1 , V I B 2 )  

Example 1: Calculation for OPA205 Maximum Bias Current to Input Offset Voltage

OPA206 Circuit for IB Example Calculation Figure 2-3 Circuit for IB Example Calculation
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IB Input bias current OPA205A 25°C ±0.1 ±0.5 nA
IOS Input offset current OPA205A 25°C ±0.1 ±0.4 nA
Equation 24. V I B 1 = 0.5 n A + 0.4 n A 2 ( 0.99 k Ω ) - 0.5 n A - 0.4 n A 2 ( 10 k Ω ) = - 2.31 μ V
Equation 25. V I B 2 = 0.5 n A - 0.4 n A 2 ( 0.99 k Ω ) - 0.5 n A + 0.4 n A 2 ( 10 k Ω ) = - 6.70 μ V
Equation 26. V I B = m a x ( - 6.70 μ V , - 2.31 μ V )   =     6.70 μ V